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preliminary a intel 450kx/gx pciset the information in this document is subject to change.
preliminary a information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of intel products. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications before placing your product order. third party brands and names are the property of their respective owners. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation 1996
preliminary iii a contents chapter 1 intel 450kx/gx pciset overview 1.0 intel 450kx pciset ....................................................................................................................................5 2.0 intel 450GX pciset ....................................................................................................................................6 3.0 host bus efficiency ..................................................................................................................................6 4.0 system memory map ................................................................................................................................7 4.1 compatibility area ...............................................................................................................................8 4.2 extended memory (isa) .....................................................................................................................9 4.3 extended memory (eisa) .................................................................................................................10 4.4 extended memory (above 4 gbytes) ................................................................................................12 4.5 system management mode (smm) ..................................................................................................12 5.0 i/o space (pb only) ................................................................................................................................12 6.0 memory mapped i/o ...............................................................................................................................13 chapter 2 82454kx/gx pci bridge (pb) 1.0 pb signal descriptions ..........................................................................................................................19 1.1 pb signals .......................................................................................................................................19 1.2 signal state during reset ................................................................................................................25 2.0 pb register description ........................................................................................................................26 2.1 initialization and configuration ..........................................................................................................26 2.2 i/o space registers ..........................................................................................................................27 2.2.1 confaddconfiguration address register ........................................................................28 2.2.2 trcturbo and reset control ............................................................................................29 2.2.3 confdataconfiguration data register ............................................................................30 2.3 pci configuration space ..................................................................................................................30 2.4 pb pci configuration registers .......................................................................................................32 2.4.1 vidvendor identification register .......................................................................................34 2.4.2 diddevice identification register .......................................................................................34 2.4.3 pcicmdpci command register .......................................................................................34 2.4.4 pcistspci status register ...............................................................................................35 2.4.5 ridrevision identification register ....................................................................................36 2.4.6 classcclass code register ............................................................................................36 2.4.7 clsizecache line size register ......................................................................................36 2.4.8 pltmrpci latency timer ..................................................................................................37 2.4.9 headtheader type register .............................................................................................37 2.4.10 bistbist register ..............................................................................................................37 2.4.11 tsmtop of system memory register ...............................................................................38 2.4.12 pdmpci decode mode ....................................................................................................38
iv preliminary a 2.4.13 bdnum?bridge device number register ..........................................................................39 2.4.14 pbnum?pci bus number register ...................................................................................39 2.4.15 psbnum?subordinate bus number register ...................................................................40 2.4.16 pbc?pb configuration register .........................................................................................40 2.4.17 dcc?deturbo counter register .........................................................................................41 2.4.18 crwc?cpu read/write control register .........................................................................41 2.4.19 prwc?pci read/write control .........................................................................................42 2.4.20 smme?smram enable register .......................................................................................43 2.4.21 vbae?video buffer area enable register .........................................................................43 2.4.22 pam[0:6]?programmable attribute map register ...............................................................44 2.4.23 errcmd?error reporting command register .................................................................45 2.4.24 errsts?error reporting status register .........................................................................45 2.4.25 mgr?memory gap range register ..................................................................................46 2.4.26 mgua?memory gap upper address register ...................................................................46 2.4.27 pfb?pci frame buffer register .........................................................................................47 2.4.28 hmgsa?high memory gap range start address register ..............................................48 2.4.29 hmgea?high memory gap end address register ...........................................................48 2.4.30 iosr1?i/o space range 1 register (82454gx only) .......................................................49 2.4.31 pcirsr?pci reset register .............................................................................................49 2.4.32 iosr2?i/o space range 2 register (82454gx only) .......................................................50 2.4.33 apicr?i/o apic range register ......................................................................................50 2.4.34 confvr?configuration values driven on reset register ................................................51 2.4.35 csconfv?captured system configuration values register ............................................52 2.4.36 smmr?smram range register .......................................................................................53 2.4.37 hbiosr?high bios range register .................................................................................53 2.4.38 exerrcmd?pb extended error reporting command register ......................................53 2.4.39 exerrsts?pb extended error reporting status ............................................................55 2.4.40 pbrtmr?pb retry timers ................................................................................................56 3.0 pb functional description ....................................................................................................................57 3.1 memory and i/o map ........................................................................................................................57 3.1.1 memory address map ............................................................................................................57 3.1.2 i/o address map ....................................................................................................................59 3.2 host bus interface ............................................................................................................................60 3.3 pci bus interface ..............................................................................................................................61 3.4 data integrity and error handling .....................................................................................................62 3.4.1 host bus errors ......................................................................................................................62 3.4.2 pci bus errors .......................................................................................................................62 3.4.2.1 pb master operation on pci ....................................................................................63 3.4.2.2 pb target operation on pci .....................................................................................63 3.5 dual pb architectures (82454gx only) ............................................................................................65
preliminary v a 3.6 peripheral operation and performance ............................................................................................68 3.6.1 matching peripherals to the 450kx/gx .................................................................................68 3.6.2 distributing peripherals within the i/o subsystem .................................................................69 3.6.3 pci-to-pci bridges ................................................................................................................69 3.6.4 bios performance tuning ......................................................................................................69 3.7 clock, reset, and configuration .......................................................................................................70 3.7.1 system clocking .....................................................................................................................70 3.7.1.1 host bus clock .........................................................................................................70 3.7.1.2 pci clock ..................................................................................................................71 3.7.2 system reset .........................................................................................................................71 3.7.3 system initialization ...............................................................................................................72 3.7.4 dual pb configuration (82454gx only) .................................................................................72 3.7.5 using the 82379ab sio.a pci-to-isa bridge with the 450kx/gx .........................................73 3.8 host to pci bus command translation ............................................................................................76 3.9 pci to host bus command translation ............................................................................................77 4.0 pb pinout and package information .....................................................................................................79 4.1 pin assignment .................................................................................................................................79 4.2 package information .........................................................................................................................87 chapter 3 memory controller (mc) 1.0 mc signal description ...........................................................................................................................93 1.1 dc signals ........................................................................................................................................93 1.2 dp signals ........................................................................................................................................96 1.3 mic signals ......................................................................................................................................98 1.4 signal state during reset ..............................................................................................................100 2.0 mc register description ......................................................................................................................101 2.1 initialization and configuration ........................................................................................................101 2.2 i/o space registers ........................................................................................................................102 2.2.1 confaddconfiguration address register ......................................................................103 2.2.2 confdataconfiguration data register ..........................................................................103 2.3 mc configuration registers ............................................................................................................104 2.3.1 vidvendor identification register .....................................................................................105 2.3.2 diddevice identification register .....................................................................................105 2.3.3 pcicmdpci command register .....................................................................................106 2.3.4 pcistspci status register .............................................................................................106 2.3.5 ridrevision identification register ..................................................................................106 2.3.6 classcclass code register ..........................................................................................107 2.3.7 baseaddmc base address register (450GX only) .......................................................107 2.3.8 cdnumcontroller device number register ....................................................................108 2.3.9 cmdcommand register ..................................................................................................108
vi preliminary a 2.3.10 smme?smram enable register .....................................................................................110 2.3.11 vbre?video buffer region enable register ...................................................................110 2.3.12 pam[0:6]?programmable attribute map registers ...........................................................110 2.3.13 drl?dram row limit (0 to 7) .........................................................................................111 2.3.14 sbcerradd?single bit correctable error address register .........................................112 2.3.15 mg?memory gap register ..............................................................................................113 2.3.16 mgua?memory gap upper address register .................................................................114 2.3.17 lmg?low memory gap register .....................................................................................114 2.3.18 hmgsa?high memory gap start address register ........................................................115 2.3.19 hmgea?high memory gap end address register .........................................................115 2.3.20 apicr?i/o apic range register ....................................................................................115 2.3.21 uerradd?uncorrectable error address register ..........................................................116 2.3.22 memtim?memory timing register ..................................................................................116 2.3.23 smmr?smram range register .....................................................................................119 2.3.24 hbiosr?high bios gap range register .......................................................................119 2.3.25 merrcmd?memory error reporting command ............................................................120 2.3.26 merrsts?memory error status register ......................................................................120 2.3.27 serrcmd?system error reporting command register ................................................121 2.3.28 serrsts?system error status register ........................................................................122 2.4 memory configuration determination algorithm .............................................................................122 3.0 mc functional description ..................................................................................................................123 3.1 memory and i/o map ......................................................................................................................123 3.2 host bus interface ..........................................................................................................................124 3.3 dram interface ..............................................................................................................................125 3.3.1 dram configurations ..........................................................................................................127 3.3.1.1 memory interface component (mic) ......................................................................127 3.3.1.2 4-way dram configuration (450GX only) .............................................................128 3.3.1.3 2-way dram configuration ....................................................................................129 3.3.1.4 non-interleaved dram configuration .....................................................................130 3.4 clocks and reset ............................................................................................................................131 3.4.1 clocks ..................................................................................................................................131 3.4.2 reset ....................................................................................................................................131 4.0 mc pinout and package information ..................................................................................................132 4.1 82453kx/82453gx (dc) pin assignment ......................................................................................132 4.2 82452gx/82452kx (dp) pin assignment ......................................................................................135 4.3 82451gx/82451kx (mic) pin assignment .....................................................................................142 4.4 82453gx/82453kx (dc) package dimensions ..............................................................................145 4.5 82452gx/82452kx (dp) package dimensions ..............................................................................146 4.6 82451gx/82451kx (mic) package dimensions ............................................................................148
preliminary vii a chapter 4 pciset electrical specifications 1.0 electrical characteristics ....................................................................................................................151 1.1 test pins and unused pins .............................................................................................................151 1.2 signal groups .................................................................................................................................151 1.2.1 the power good signal pwrgd .....................................................................................152 1.3 maximum ratings ...........................................................................................................................153 1.4 dc specifications ...........................................................................................................................154 1.5 ac specifications ............................................................................................................................157 1.5.1 waveforms ...........................................................................................................................160 2.0 signal quality .......................................................................................................................................162 2.1 i/o signal simulationsensuring i/o timings ...............................................................................162 2.2 signal quality specifications ..........................................................................................................163 2.3 pciset ringback specification ........................................................................................................163 2.4 450kx/gx undershoot specification ..............................................................................................165 3.0 thermal specifications ........................................................................................................................166 index alphabetized index ....................................................................................................................................169
viii preliminary a
preliminary 1 a pciset overview chapter 1 intel 450kx/gx pciset overview
2 preliminary pciset overview a
a pciset overview preliminary 3 pciset product overview n pciset host bus support supports pentium a pro processor at 60 mhz, and 66 mhz bus speeds 64-bit data and 36-bit address bus parity protection on control signals dual-processor support (450kx) up to eight deep in-order queue four deep outbound request queue four cache line read and write buffers gtl+ bus driver technology n host-to-pci bridge (pb) combines both the control and data path in a single chip synchronous pci interface 32-bit address/data pci bus (64-bit dual cycle address support) parity protection on all pci bus signals four deep inbound request queue data collection/write assembly of line bursts. support for 3.3v & 5v pci devices available in 304 pin qfp or 352 pin bga ecc protection on host data bus (450GX) quad-processor support (450GX) internal bridge arbiter for two pbs in a system (450GX) n memory controller (mc) 1 gb maximum memory (450kx) 2-way interleaved and non- interleaved memory organizations supports 3.3v and 5v simms supports standard 32- or 36-bit simms or 72-bit dimms supports 4 mbit, 16 mbit, and 64 mbit dram technology single bit error correction, double bit and nibble error detection memory array power management recovers dram memory behind programmable memory gaps read page hit 8-1-1-1 (at 66 mhz, 60 ns dram) read page miss 11-1-1-1 (66 mhz, 60 ns dram) read page miss + precharge 14-1-1- 1 (66 mhz, 60 ns dram) available in 208-pin qfp for the dc; 240-pin qfp or 256-pin bga for the dp; 144-pin qfp for the mic n on-chip digital pll (both pb and mc) n test support (jtag) (both pb and mc) 4 gbs maximum main memory (per 82453gx) 4-way and 2-way interleaved, and non-interleaved memory organizations (450GX) up to two mcs in a system (450GX) this document describes both the intel 450kx and 450GX pcisets. unshaded areas apply to both the pcisets. shaded areas, like this one, describe the 450GX operations that differ from the 450kx. the intel 450kx/gx pcisets provide a high-performance system solution for pentium a pro processor-based pci systems by combining high integration, high performance technology with a scalable architecture that is capable of high throughput for up to four pentium pro processors. scalability provides a wide range of system solutions from cost-effective uniprocessor systems to high-end multiprocessor systems without sacrificing performance. for systems requiring extensive i/o (e.g., file servers), a second pb can be easily added providing two high-performance pci bus structures. the flexibility of the memory controller permits easy expansion from a simple non-interleaved organization to a 2-way or 4-way interleaved organization to increase performance. extended error checking and logging, ecc, and the ability to build in redundancy (e.g, multiple processors and dual pci bridges) provides a comprehensive solution for systems requiring high reliability. the pciset may contain design defects or errors known as errata. current characterized errata are available upon request.
4 preliminary pciset overview a figure 1. 450kx/gx simplified system block diagram pb pci bus main memory mic dc dp mc pentium a pro (1 gbyte max) pb pci bus (x4) pci-to-isa bridge isa device isa device pci device isa bus host bus pci device pci device pci device (4 gbyte max) pci-to-eisa bridge eisa device isa device eisa device eisa bus internal arbitration apic bus note: 450kx: supports one pb, one mc, and up to two processors. 450GX: supports up to two pbs, two mcs, and four processors on the host bus. pentium a pro pentium a pro pentium a pro processor processor processor processor main memory mic dc dp mc (4 gbyte max) (x4) pb
preliminary 5 a pciset overview 1.0 intel 450kx pciset the 450kx desktop pciset consists of the 82454kx pci bridge (pb) and the memory controller (mc). the mc consists of the 82453kx dram controller (dc), the 82452kx data path (dp), and four 82451kx memory interface components (mic). the system configuration using the intel 450kx pciset supports one pb, one mc and up to two pentium pro processors (figure 1). an isa subsystem is also located below the pb. for pentium pro processor bus error detection, the 450kx generates and checks parity over the address and request/response signal lines. this feature can be enabled/disabled during system configuration. kx pci bridge (pb) the pb is a single-chip host-to-pci bridge. a rich set of cpu-to-pci and pci-to-cpu bus transaction transla- tions optimize bus bandwidth and improve system performance. all isa and eisa regions are supported. three programmable memory gaps can be createda pci frame buffer region with specialized frame buffer attributes and two general-purpose memory gaps (called the memory gap region and the high memory gap region). the pb takes advantage of the pentium pro processor ratio clocking scheme to assure modularity now and upgradability in the future. the pb has a synchronous interface to the pentium pro processor bus and supports a derived clock for the synchronous pci interface. the pb derives either a 30 or 33 mhz pci clock output from the pentium pro processor bus clock. the pb pci signals are 5 volt tolerant and can be used with either 5 volt or 3.3 volt pci devices. kx memory controller (mc) the combined mc (dc, dp, and four mics) act as one physical load on the pentium pro processor bus. the dc provides control for the dram memory subsystem, the dp provides the data path, and the four mics are used to interface the mc datapath with the dram memory subsystem. the memory configuration can be either 2-way interleaved or non-interleaved. both single-sided and double- sided simms are supported. dram technologies up to 64 mbits at speeds of 50ns, 60ns, and 70ns can be used. asymmetric dram is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 column address lines). the maximum memory size is 1 gbyte for the 2-way interleaved configuration and 512 mbytes for the non-interleaved configuration using 16 mbit technology. in addition to these memory configurations, the mc provides data integrity features including ecc in the memory array. these features, as well as a set of error reporting mechanisms, can be selected via configuration of the mc. each interleave provides a 64-bit data path to main memory (72-bits including ecc). the mc is pc compatible. all isa and eisa regions are decoded and shadowed based on programmable configurations. regions above 1 mbyte with size 1 mbyte or larger that are not mapped to memory may be reclaimed by setting the appropriate configuration in the mc. three programmable memory gaps can be created and are called the low memory gap region , the memory gap region and the high memory gap region .
6 preliminary pciset overview a 2.0 intel 450GX pciset 3.0 host bus efficiency the pentium pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans- actions. a single pentium pro processor may have up to four transactions outstanding at the same time, and can be configured to support up to eight transactions active on the pentium pro processor bus at any one time. the pb and mc support a choice of one or eight active transactions on the pentium pro processor system bus at one time (in-order queue depth). the number of transactions that can target a particular bus client is configured separately from the total number of transactions allowed on the bus. each pb can accept up to four transactions into its outbound request queue that target its associated pci bus. the pb also contains a four deep inbound queue that holds pci initiated requests directed to the pentium pro processor bus. each mc can accept up to four transactions that target its associated memory space. the intel 450GX pciset includes the features discussed for the intel 450kx pciset and provides the additional capabilities described in this section. this pciset consists of the 82454gx pci bridge (pb) and the memory controller (mc). the mc for the 450GX consists of the 82453gx dram controller (dc), the 82452gx data path (dp), and four 82451gx memory interface controllers (mic). the 450GX permits two pbs and two mcs in a system. in addition to parity support on the host bus described for the 450kx, the 450GX generates and checks ecc over the host data lines. this feature can be enabled/disabled during configuration. one aspect of the 450GX is that it can be used as a drop-in replacement for an 450kx design. additional pins are added in such a way that proper wiring of 450kx test pins (gtlhi, testlo, and testhi) will allow an 450GX to operate in the same system while functioning exactly as an 450kx. gx pci bridge (pb) two 82454gx pbs can be used in a system. dual pbs provide a modular approach to i/o performance improvements. compatibility versus speed are addressed with an optional compatibility operating mode to guarantee standard bus compatible operation when needed, and allow bus concurrency when possible. in a dual pb system, one pb is configured by strapping options at power-up to be the compatibility pb . this pb provides the pc compatible path to boot rom and the isa/eisa bus. the second pb is configured by the strapping options to be the auxiliary pb . the compatibility pb is the highest priority bridge to ensure a proper response time for isa bus masters. when two pbs are on the host bus, the compatibility pb handles arbitration with an internal arbiter. gx memory controller (mc) the memory configuration can be either 4-way interleaved, 2-way interleaved, or non-interleaved. both single- sided and double-sided simms are supported. dram technologies up to 64mbit at speeds of 50ns, 60ns, and 70ns can be used. asymmetric dram is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 column address lines). the maximum memory size is 4 gbytes for the 4-way interleaved configuration, 2 gbytes for the 2-way interleaved configuration, and 1 gbyte for the non-interleaved configuration using 64 mbit technology. the mc provides a 64-bit data path to main memory (72-bits including ecc) for each interleave (288 bits for a 4-way interleave design).
preliminary 7 a pciset overview both the pb and mc provide four 32-byte buffers for outbound data and four 32-byte buffers for inbound data. for the pb, the outbound data refers to cpu-to-pci writes or pci reads from the cpu bus and inbound data refers to pci-to-cpu writes or cpu reads from pci. for the mc outbound data refers to cpu writes to main memory and inbound data refers to cpu reads of main memory. the maximum data transfer that is supported by the pentium pro processor bus is four 64-bit wide transfers. this transfer satisfies the 32-byte cache line size of the pentium pro processor interface. the pentium pro processor supports operations that are not completed in the order in which they were requested. this deferred response capability allows the pentium pro processor bus to be freed to execute other requests while waiting for the response from a request to a device with relatively long latency. note that the 450 pciset does not defer requests to itself, nor does it (the pb) allow its transactions to be deferred. 4.0 system memory map a pentium pro processor system can have up to 64 gbytes of addressable memory. the lower 1 mbyte of this memory address space is divided into regions that can be individually controlled with programmable attributes such as disable, read/write, write only, or read only. at the highest level, the address space is divided into four conceptual regions as shown in figure 2. these are the 0C1 mbyte compatibility area, the 1 mbyte to 16 mbyte extended memory region used by isa, the 16 mbyte to 4 gbyte extended memory region used by eisa, and the 4 gbyte to 64 gbyte extended memory introduced by 36 bit addressing. each of the regions are divided into subregions, as described in the following sections. figure 2. pentium pro processor memory address space. for the 450GX, up to two mcs can be placed in the address space spanned by these regions. in a pc archi- tecture, the only restrictions on memory placement are that there be memory starting at address 0 and that there be enough memory to operate a system. the mcs in a system need not have contiguous address spaces. each mc also supports two memory ranges for the memory connected to the mc, by providing a high memory gap range register that defines the space between the two ranges of memory. this range effectively defines the top address for the lower memory range and the base address for the upper memory range. compatibility area extended memory (isa) extended memory (eisa) 1mb 15mb 4gb - 16mb 100_0000 0 f_ffff ff_ffff 10_0000 extended memory (above 4gb) 64gb - 4gb f_ffff_ffff 1_0000_0000 ffff_ffff
8 preliminary pciset overview a 4.1 compatibility area the first region of memory is called the compatibility area because it was defined for early pcs. this region is divided into 5 subregions, as shown in figure 3. figure 3. expanded view of compatibility area. dos region the dos region is 640 kbytes in the address range 00000hC9ffffh. dos applications execute here. this region is further divided into two parts. the 512 kbyte area at 00000hC7ffffh is always mapped to memory on the pentium pro processor bus (enabled in the mc), while the 128 kbyte area from 80000hC9ffffh can be mapped to memory on the pentium pro processor bus or pci memory (enabled in the pb). this region can be programmed as disabled, read/write, write only, or read only. graphics adapter memory the 128 kbyte graphics adapter memory region at a0000hCbffffh is normally mapped to a video device on the pci bus. typically, this is a vga controller. if there are no graphics compatible devices, this region can be used as system memory. the range a0000hCaffffh (64 kbytes) is also the default region for smm space. the smm region can be re-mapped by programming the smm range register in the pb and mc. isa expansion the 128 kbyte isa expansion region is divided into eight 16 kbyte blocks that can be independently programmed as disabled, read/write, write only, or read only providing the capability to shadow these regions in main memory. typically, these blocks are mapped through the pb to isa space. system bios extended system bios isa video bios graphics adapter isa window / memory dos area 64kb 64kb 128kb 128kb 640kb 0 a_0000 c_0000 e_0000 f_0000 f_ffff isa expansion/ dos region channel i/o memory 8_0000 c_8000 memory compatibility area extended memory (isa) extended memory (eisa) 1mb ffff_ffff 100_0000 0 f_ffff ff_ffff 10_0000 extended memory (above 4gb) f_ffff_ffff 1_0000_0000
preliminary 9 a pciset overview historically, the 32 kbyte region from c0000hCc7fffh has contained the video bios located on a video card in the isa expansion area. however, in the high integration portable and desktop market video bios is more likely to be located in the extended system bios or system bios regions that start at e0000h. the 96 kbyte area from c8000hCdffffh has usually been made available to expand memory windows in 16 kbyte blocks, depending on the requirements of other channel devices in the corresponding isa space. more recently, pcmcia devices for the portable market have been assigned within this region. this region could also be used as system management mode (smm) memory. extended system bios this 64 kbyte region from e0000hCeffffh is divided into four 16 kbyte blocks and may be mapped either to the memory controller or the pci bridge. this region can be programmed as disabled, read/write, write only, or read only, providing the capability to shadow these regions in main memory. typically, this area is used for ram or rom. system bios the 64 kbyte region from f0000hCfffffh is treated as a single block. after power-on reset, the pb (compat- ibility pb in an 450GX dual pb system) has this area r/w enabled to respond to fetches during system initial- ization. the mc(s) and auxiliary pbs (450GX pciset) have this area r/w disabled. this region can be programmed as disabled, read/write, write only, or read only, providing the capability to shadow these regions in main memory. 4.2 extended memory (isa) the isa extended memory region in figure 4 covers 15 mbytes ranging from 100000hCffffffh. there are three programmable ranges that may be mapped to the isa extended memory region of the mcthe low memory gap range, the memory gap range, and the high memory gap range. memory in these ranges, that would normally be lost, is recovered by the mc by extending the effective top of system memory, if reclaiming is enabled. the memory gap range and high memory gap range are also programmable ranges in the pb. the pb also has a programmable pci frame buffer range. low memory gap range (mc only) the low memory gap range can start on any 1 mbyte boundary in the isa or eisa extended memory region, and can be 1, 2, 4, 8, 16, or 32 mbytes. this region defines a hole in system dram space where accesses can be directed to the pci bus. the low memory gap range is used by isa devices such as lan or linear frame buffers which are mapped into the isa extended region, or by any eisa or pci device. the low memory gap range must reside at the lowest address of the three memory gaps, if it is enabled. pci frame buffer range (pb only) the pci frame buffer range can start on any 1 mbyte boundary in either the isa extended memory region or the eisa extended memory region, and can be 1, 2, 4, 8, 16,or 32 mbytes.
10 preliminary pciset overview a memory gap range (mc and pb) the memory gap range can start on any 1 mbyte boundary, above 1 mbyte, and can 1, 2, 4, 8, 16, or 32 mbytes. this region defines a hole in system dram space where accesses can be directed to the pci bus. the memory gap range is used by isa devices such as lan or linear frame buffers which are mapped into the isa extended region, or by any eisa or pci device. the memory gap range must reside above the low memory gap range and below the high memory gap range, if it is enabled. high memory gap range (mc and pb) the high memory space gap can start on any 1 mbyte boundary in either the isa extended memory region, eisa extended memory region, or the extended memory region above 4gbyte, and can extend up to 64 gigabytes. it is defined by specifying a start and end address, both on 1 mbyte boundaries. the high memory gap range is provided as additional support for memory mapped i/o. the high memory gap range must reside at the highest address of the three memory gap range registers, if it is enabled. figure 4. expanded view of extended memory (isa) 4.3 extended memory (eisa) the eisa extended memory region covers the 16 mbyte to 4 gbyte range (1000000hCffffffffh). this region is divided into three sectionssystem bios, apic configuration space, and system memory. the apic configuration space is contained within the system memory region (figure 5). the low memory gap, memory gap, and high memory gap ranges can also be enabled in this region. 15mb system memory (memory or pci) 10_0000 ff_ffff compatibility area extended memory (isa) extended memory (eisa) ffff_ffff 100_0000 0 f_ffff ff_ffff 10_0000 extended memory (above 4gb) f_ffff_ffff pb only mc only note: if the pci frame buffer range is enabled in the pb (accesses forwarded to pci), the low memory gap in the mc can be used to create a gap in main memory for the corresponding memory address range (mc ignores these accesses). high memory gap range memory gap range pci frame buffer range low memory gap range
preliminary 11 a pciset overview . figure 5. expanded view of extended memory (eisa). system bios the top 2 mbytes of the eisa extended memory region is used for system bios (high bios). this is where the pentium pro processor begins execution after reset. if the pci bus is bridged to an isa bus, this region is aliased to the top 128 kbyte of the isa extended memory range. the actual address space required for system bios is less than 2 mbytes. however, the minimum pentium pro processor mttr range for this region is 2 mbytes. this establishes the minimum size for this gap. the mc supports enabling or disabling this region for access to the mc memory via the hbiosr register. i/o apic configuration space the fec00000h (4gb minus 20 mb) to fec0ffffh range is reserved for apic configuration space which includes the default i/o apic configuration space. note that there is no i/o apic unit in either the mc or pb. the default local apic configuration space is fee00000hCfee00fffh. pentium pro processor accesses to the local apic configuration space do not result in external bus activity since the local apic configuration space is internal to the pentium pro processor. however, an mtrr must be programmed to make the local apic range uncacheable (uc). the local apic base address in each pentium pro processor should be relocated to the fec00000h (4gb minus 20 mb) to fec0ffffh range so that one mtrr can be programmed to 64 kbyte for the local and i/o apics. system bios i/o apic 128kb 100_0000 fec0_0000 feco_ffff fffe_0000 ffff_ffff system memory (memory/pci) configuration space compatibility area extended memory (isa) extended memory (eisa) ffff_ffff 100_0000 0 f_ffff ff_ffff 10_0000 extended memory (above 4gb) f_ffff_ffff system memory (memory/pci) 64kb pb only mc only note: if the pci frame buffer range is enabled in the pb (accesses forwarded to pci), the low memory gap in the mc can be used to create a gap in main memory for the corresponding memory address range (mc ignores these accesses). high memory gap range memory gap range pci frame gap range low memory gap range
12 preliminary pciset overview a i/o apic units (there should be at least one for each i/o subsystem) are located beginning at the default base address fec00000h. the first i/o apic (unit #0) is at fec00000h. each i/o apic unit is located at fec0x000h where x is i/o apic unit 0 through f. the address range between the apic configuration space and the high bios (fed00000hCffdfffffh) is always mapped to local memory unless the range is above top of physical memory or the high bios and apic range are disabled in the pb and the range falls within a memory gap range. the mc supports enabling or disabling this region for access to the mc memory via the i/o apic range register. 4.4 extended memory (above 4 gbytes) the extended memory region is from 4 gbyte to 64 gbyte (100000000hCfffffffffh). the pb and mc can be mapped into this range. the memory gap range and high memory gap range are both available for use within the extended memory region (above 4 gbyte). 4.5 system management mode (smm) a pentium pro processor asserts smmem# in its request phase if it is operating in system management mode. sm code resides in sm memory space. sm memory can overlap with memory residing on the pentium pro processor bus or memory normally residing on the pci bus. the mc and pb determine where sm memory space is located through the value programmed in their respective smm range registers. 5.0 i/o space (pb only) the pb optionally supports isa expansion aliasing (figure 6). when isa expansion aliasing is enabled, the ranges designated as i/o expansion are internally aliased to the 100C3ffh range before the i/o space range registers are checked. note that all devices on the pentium pro processor bus that are mapped into i/o space must have i/o aliasing consistently enabled/disabled. for the intel 450GX pciset, the pb allows i/o addresses to be mapped to the pentium pro processor bus or through designated bridges in a multi bridge system. two i/o space range registers allow the pb to decode two i/o address ranges. if the address range is enabled, transactions targeting that range are forwarded to the pci bus. if the address range is disabled, the transaction is ignored.
preliminary 13 a pciset overview 6.0 memory mapped i/o the pb allows memory addresses to be mapped to the host bus, or for the 450GX pciset, through the other bridge in a dual pb system. memory mapped i/o devices can be located anywhere in the 64 gbyte address space. the frame buffer range allows the pb to decode memory mapped i/o space extending up to 4 gbyte. the memory space gap and high memory gap registers allow the pb to decode two address ranges extending up to 64 gbytes. figure 6. view of i/o space 0000 ffff . . . 0000 ffff i/o space gap 2 remaining i/o space i/o space 3ff 400 isa alias mode disabled isa alias mode enabled 100 isa expansion i/o space 7ff 800 500 i/o space bff c00 900 isa expansion i/o space (aliased to 100-3ff) isa expansion (aliased to 100-3ff) and aliases note: the compatibility pb defaults to claiming all i/o transactions. if a range is enabled in the auxiliary pb, the same range must be disabled in the compatibility pb. i/o space gap 1 i/o space gap 2 i/o space gap 1
14 preliminary pciset overview a
preliminary 15 a 82454kx/gx (pb) chapter 2 82454kx/gx pci bridge (pb)
16 preliminary 82454kx/gx (pb) a
a 82454kx/gx (pb) preliminary 17 82454kx/gx pci bridge (pb) n supports the pentium a pro processor at 60 mhz and 66 mhz bus speeds n pci specification 2.0 compliant n 64-bit data bus and 36-bit address bus n parity protection on control signals n up to eight deep in-order queue n four deep outbound request queue n dual-processor support (450kx) n four cache line size read and write buffers n gtl+ host bus interface n synchronous pci interface ecc protection on data bus (450GX) quad-processor support (450GX) n 32-bit address/data pci bus (64-bit dual cycle address support) n parity protection on all pci bus signals n four deep inbound request queue n data collection/write assembly of line bursts. n single chip: combined controller and data path in a 304-pin qfp or 352 bga n support for 3.3v and 5v pci devices n on-chip digital pll (dpll) n component and in-system connectivity test support (jtag) internal bridge arbiter for two pbs in a system (450GX) the 82454kx/gx pb are single-chip pc-compatible host-to-pci bridges. a rich set of host-to-pci and pci-to- host bus transaction translations optimize bus bandwidth and improve system performance. all isa and eisa regions are supported. three programmable memory gaps can be createda pci frame buffer region and two general-purpose memory gaps (the memory gap region and the high memory gap region). the pb has a synchronous interface to the pentium pro processor bus and supports a derived clock for the synchronous pci interface. the pb generates and checks ecc over the host data bus (82545gx only), and generates and checks parity over the address and request/response signal lines (both 82454kx and 82454gx). the pb also checks address and data parity on the pci bus. for the 82454gx, two pbs can be used in a system. the intel 450kx/gx pcisets may contain design defects or errors known as errata. current characterized errata are available upon request. this document describes both the 82454kx and 82454gx pbs. unshaded areas describe features common to the 82454kx and 82454gx. shaded areas, like this one, describe the 82454gx operations that differ from the 82454kx.
18 preliminary 82454kx/gx (pb) a figure 1. 82454kx/gx simplified block diagram gray areas indicate gx only pins host bus interface pci interface bpri# ads# lock# a[35:3]# req[4:0]# rp# ap[1:0]# aerr# bnr# hit# hitm# defer# rs[2:0]# rsp# trdy# drdy# dbsy# d[63:0]# dep[7:0]# flush# berr# binit# smiact# ad[31:0] c/be[3:0]# ptrdy# stop# plock# devsel# pa r irdy# frame# perr# serr# preq# pgnt# memreq# flshbf# memack# clock, reset and support bridge to bridge sideband ioreq# iognt# gtlrefv bclk reset# creset# init# pclkin pclk pwrgd pcirst# te s t tck tdi tdo tms trst# testlow recven
preliminary 19 a 82454kx/gx (pb) 1.0 pb signal descriptions this section contains a detailed description of each signal. the signals are arranged in functional groups according to their interface. note that the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when # is not present at the end of a signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of active-low and active-high signals. the term assert , or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate , or negation indicates that a signal is inactive. the following notations are used to describe the signal type. i input is a standard input-only signal. o to t e m pole output is a standard active driver. i/o input/output is bi-directional, tri-state signal. gtl+ gtl+ processor bus signal defined for 1.5v operation. cmos rail-to-rail cmos tolerant to 5v levels. pci cmos signal specifically meeting pci specification 2.0. analog reference voltage. 1.1 pb signals table 1. host bus interface signals signal type description a[35:3]# i/o, gtl+ address bus. a[35:3]# contains the transaction address on the clock cycle with ads# asserted. byte enables, deferred id, and additional transaction information are encoded on these lines during the cycle following ads#. note that the pb never asserts defer enable when it is a bus master. ads# i/o, gtl+ address strobe. ads# is asserted during the first cycle of the request phase to indicate valid address and command signals. aerr# i/o, gtl+ address error. aerr# is asserted by any agent that detects an address parity error, if enabled in the exerrcmd register. ap[1:0]# i/o, gtl+ address parity. ap1# covers a[35:24]# and ap0# covers a[23:3]#. ap[1:0]# is valid on both cycles of the request. berr# i/o, gtl+ bus error. berr# is asserted by any agent that observes an unrecoverable bus protocol violation, if enabled in the exerrcmd register. binit# i/o, gtl+ bus initialization. binit# is asserted to re-initialize the bus. the pb terminates any ongoing pci transaction at this time and resets its inbound and outbound queues. no configuration registers or error logging registers are affected. bnr# i/o, gtl+ block next request. bnr# is asserted by an agent to prevent the request bus owner from issuing further requests. bpri# i/o, gtl+ priority agent bus request. bpri# is issued by the high priority bus agent to acquire the request bus. the high priority agent is always the next bus owner.
20 preliminary 82454kx/gx (pb) a d[63:0]# i/o, gtl+ data bus. the data bus consists of eight bytes. all bytes are valid for line transfers. the valid bytes are determined by the byte enables that are asserted in the second cycle of the request phase. dbsy# i/o, gtl+ data busy. dbsy# is asserted by the data bus owner to hold the data bus for the next cycle. dbsy# is not asserted for single cycle transfers. defer# i/o, gtl+ defer. defer# is driven by the addressed agent to indicate that the transaction cannot be guaranteed bus completion. dep[7:0]# i/o, gtl+ data ecc. on the host bus, dep[7:0]# are used for ecc on the d[63:0]# signals. drdy# i/o, gtl+ data ready. drdy# is driven by the data bus owner for each cycle that contains valid data. drdy# is negated to indicate idle cycles during the data phase. flush# o, cmos flush. the pb asserts flush# to cause the processor to stop caching new lines, writeback all cache lines in the modified state, and disable further caching until flush# is negated. in an 82454gx dual pb system this signal is only available on the compatibility pb and is not available on the auxiliary pb. hit# i/o, gtl+ hit. the pb asserts hit# and hitm# together to extend the snoop window of a transaction targeting its pci bus. since the pb is not a caching agent, it never asserts hit# alone. hitm# i/o, gtl+ hit modified. the pb asserts hit# and hitm# together to extend the snoop window of a transaction targeting its pci bus. since the pb is not a caching agent, it never asserts hitm# alone. lock# i/o, gtl+ lock. the lock# signal is asserted for an indivisible sequence of transactions. req[4:0]# i/o, gtl+ request type. req[4:0]# contain the command on the clock with ads# asserted and data size/length information on the next clock. rp# i/o, gtl+ request parity. rp# is even parity that covers req[4:0]# and ads#. rp# is valid on both cycles of the request. rs[2:0]# i/o, gtl+ response. rs[2:0]# encode the response to a request. rsp# i/o, gtl+ response parity. rsp# provides response parity for rs[2:0]#. smiact# o, cmos smi acknowledge. smiact# is asserted when the pb detects a host smi acknowledge special transaction (regardless of its initiator) with smmem# asserted. once asserted, smiact# remains asserted until the pb detects a host smi acknowledge special transaction with smmem# negated. in an 82454gx dual pb system this signal is only available on the compatibility pb and is not available on the auxiliary pb. trdy# i/o, gtl+ target ready. trdy# is driven by the target of the data to indicate it is ready to receive data. table 1. host bus interface signals (continued) signal type description
preliminary 21 a 82454kx/gx (pb) table 2. pci interface signals signal type description ad[31:0] i/o, pci pci address/data. addresses and data are multiplexed on this bus. the physical byte address is output during the address phase and the data follows in the subsequent data phase(s). c/be[3:0]# i/o, pci bus command and byte enables. c/be[3:0]# contains commands during the address phase and byte enables during the data phase. devsel# i/o, pci device select. devsel# is driven by the device that has decoded its address as the target of the current access. flshbf# i, cmos flush buffers. this sideband signal is typically generated by a standard pci bus bridge (e.g., isa or eisa bridge) to command the pb to flush all write post buffers pointed toward the pci bus and disable further posting. once all buffers are flushed, the pb asserts memack# until flshbf# is negated. flshbf# memreq# function 0 0 no action. 01 reserved. 1 0 apic flush. flush buffers pointing toward pci. 1 1 guaranteed access time (gat) mode. guarantee pci bus immediate access to the cpu bus. flush all buffers, request queues, empty in-order queue, and retain host bus ownership. frame# i/o, pci pci frame. frame# is driven by a master to indicate the beginning and end of a transaction. irdy# i/o, pci pci initiator ready. irdy# is asserted by the master to indicate that it is able to complete the current data transfer. memack# o, cmos memory acknowledge. memack# is generated in response to flshbf# or memreq# generated by a standard bus bridge. memreq# i, cmos memory request . this sideband signal is typically generated by a standard bridge (e.g., isa or eisa bridge) to guarantee access latency from standard bus masters to main memory (see flshbf# description). once all buffers have been flushed, the pb asserts memack# continuously until memreq# is negated. par i/o, pci pci parity. par is driven to even parity across ad[31:0] and c/be[3:0]# by the master during address and write data phases. the target drives par during read data phases. perr# i/o, pci pci parity error. perr# is pulsed by an agent receiving data with bad parity one clock after par is asserted. pgnt# i, cmos pci grant. pgnt# indicates to the pb that it has been granted the pci bus. plock# i/o, pci pci lock. plock# is asserted by an agent requiring exclusive access to a target.
22 preliminary 82454kx/gx (pb) a bridge to bridge sideband signals preq# o, cmos pci request. the pb asserts preq# to the pci arbiter requesting the pci bus. ptrdy# i/o, pci pci target ready. ptrdy# is asserted by the target to indicate that it is able to complete the current data transfer. serr# o, pci pci system error. serr# is asserted by the pci bridge to alert the system of serious errors. several events (e.g., address parity errors, data parity errors, etc.) can optionally result in an serr#. in a typical system, serr# causes an nmi (e.g., by a pci-to-isa or pci-to-eisa bridge). stop# i/o, pci stop. stop# is a request from the target to stop the current transaction. table 3. bridge to bridge sideband signals signal type description iognt# i, cmos i/o grant (82454gx only). the compatibility pb is the bridge arbiter and iognt# is an input from auxiliary pb requesting ownership of the host bus. ioreq# i/o, cmos i/o request (82454gx only). the compatibility pb is the bridge arbiter and this signal is a host bus grant from the compatibility pb to the auxiliary pb. table 4. clock, reset, and support signals signal type description bclk i, cmos bus clock. bclk is the host bus clock input to the pb. all host bus timings are referenced to the rising edge of this clock. note that the bclk input to the pb must be running for 10 clocks before the assertion of pwrgd. creset# o, cmos cmos reset . creset# is a cmos version of reset#. reset# and creset# are asserted simultaneously. the negation of creset# is delayed two clocks from the negation of reset#. creset# can be used to control an external mux to select the pentium pro processor clock ratio during reset#. in an 82454gx dual pb system, this signal is only available on the compatibility pb and is not available on the auxiliary pb. gtlrefv i, analog gtl reference voltage. this voltage is the 1.0 volt reference for the gtl+ receivers. this should be created by a voltage divider from v tt (1.5v) table 2. pci interface signals (continued) signal type description the ioreq# and iognt# signals are not driven or sampled in a single bridge system. during a power-on reset, ioreq# and iognt# provide part of the pbs pci bridge device number. see section 3.7 for details.
preliminary 23 a 82454kx/gx (pb) init# o, cmos initialization. init is asserted by the pb (compatibility pb in an 82454gx dual pb system) to generate a soft reset to the processor. if init is asserted on the falling edge of reset, bist executes in the cpu before the processor boots from rom. in an 82454gx dual pb system, this signal is only available on the compatibility pb and is not available on the auxiliary pb. pcirst# o, cmos pci reset. pcirst# is asserted by the pb to reset pci bus devices for power-on reset, programmed hard reset (trc register), and programmed pci reset (pcirst register). pclk o, cmos pci clock. this signal is an output that is derived from the processor clock (derived frequency is 1/2 the host bus frequency). the derived pci clock should be externally buffered with a low skew clock driver. an external pull-down resistor is required on this signal. pclkin i, cmos pci clock input. pb reference clock for all pci bus transactions in both pb pci clock modes. all pci timing is referenced to the rising edge of this clock. pclkin is provided by an external low skew clock driver and should be coincident with pclk at the pci slots. this can be achieved by adjusting trace lengths. pwrgd i, cmos power good. pwrgd provides a power-on reset to the pb (see section 3.7). the pb asserts pcirst# when pwrgd is not asserted to tri-state the busses to prevent contention of active output buffers on the pci bus. in an 82454gx dual pb system, all pbs assert pcirst# when pwrgd is not asserted. only the compatibility pb uses pwrgd as a power-on reset. reset# i/o, gtl+ reset. the pb resets the host bus devices (asserts reset#) on power-up or when programmed through the trc register. the pb initializes its internal registers to the default values, except for the bridge device number register and the configuration driven on reset register. in an 82454gx dual pb system, only the compatibility pb drives this signal. for auxiliary pbs, this signal is an input. table 4. clock, reset, and support signals (continued) signal type description
24 preliminary 82454kx/gx (pb) a table 5. test signals signal type description gtlhi i/o gtl+ gtl test hi. these signals must be tied to v tt using a 10k w resistor for proper operation in both test and normal operating modes. tck i cmos jtag test clock. when tms is tied low, this signal has no affect on normal operation. tdi i cmos jtag test data in. when tms is tied low, this signal has no affect on normal operation. tdo o cmos jtag test data out. when tms is tied low, this signal has no affect on normal operation. testhi i/o test high. these signals must be tied high using a 10k w resistor for proper operation in both test and normal operating modes. testlo i/o test low. these signals must be tied low using a 1k w resistor for proper operation in both test and normal operating modes. tms i cmos jtag test mode select. this signal must be tied low for normal operation. trst# i cmos jtag test reset. when tms is tied low, this signal has no affect on normal operation. recven i receiver enable. useful for component test. this signal is negated with pwrgood to disable gtl+ receivers and tri-state outputs for board test.
preliminary 25 a 82454kx/gx (pb) 1.2 signal state during reset table 6 shows the state of all pb output and bi-directional signals during a hard reset (reset# asserted). notes: 1. during a power-on reset, a[12:5]# are inputs providing configuration information. for the 82454kx/gx, during a pro- grammed hard reset (via the compatibility pbs trc register), the compatibility pb drives these signals and the all other host bus devices sample these signals. 2. for the 82454gx during a power-on reset, iognt# and ioreq# are inputs used to set the pb configuration mode. 3. for the 82454gx after a power-on reset, reset# is an output from all pbs until the pbs have read in their pbid from the iognt# and ioreq# signals. after the pbs receive their pbid, reset# is an output from the compatibility pb and an input to the auxiliary pbs. 4. during a power-on reset, init# is driven inactive. the pb can be programmed (via the trc register) to drive this signal low during a programmed hard reset to invoke cpu built-in self test (bist). 5. these signals not used in the auxiliary bridge in 82450GX systems. 6. tri-state during pwrgd inactive. table 6. signal state during reset signal state signal state a[35:3]# not driven 1 ad[31:0] not driven ads# not driven aerr# not driven ap[1:0] not driven berr# not driven binit# not driven bnr# not driven bpri# not driven c/be[3:0]# not driven creset# low 5 d[63:0]# not driven dbsy# not driven defer# not driven dep[7:0]# not driven devsel# not driven drdy# not driven flush# high 5 frame# not driven hit# not driven hitm# not driven ioreq# input 2 init# high 5 irdy# not driven lock# not driven memack# not driven par not driven pcirst# low pclk driven 6 perr# not driven plock not driven preq# not driven ptrdy# not driven reset# low 3 req[4:0]# not driven rp# not driven rs[2:0]# not driven rsp# not driven serr# not driven smiact# high 5 stop# not driven tdo tri-state during trst# trdy# not driven
26 preliminary 82454kx/gx (pb) a 2.0 pb register description the pb contains two sets of registers (i/o space registers and pci configuration registers) that are accessed via the host cpu i/o address space. the i/o space registers provide access to the pci configuration registers through an indirect address scheme. the pb internal registers (both i/o space registers and pci configuration registers) are only accessible by the host bus and cannot be directly accessed by pci masters. the registers can be accessed as byte, word (16- bit), or dword (32-bit) quantities, with the exception of confadd which can only be accessed as a dword. the following nomenclature is used for access attributes. ro read only. if a register is read only, writes to this register have no effect. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. some of the pb registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, unless otherwise specified in the individual register descriptions, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with new values for other bit positions and written back. in some cases, software must program reserved bit positions to a particular value. this value is defined in the individual bit descriptions. in addition to reserved bits within a register, the pb contains address locations in the pci configuration space that are marked reserved. the pb responds to accesses to these address locations by completing the host transaction. software should not write to reserved pb configuration locations in the device-specific region (above address offset 3fh). if reset# is asserted (via either a power-on reset or by programming the trc register), the pb initializes its registers to the default value (except for the bdnum and confvr registers). the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the operating parameters and optional system features that are applicable, and to program the pb registers accordingly. the pb (compatibility pb in an 450GX system) can generate a programmed hard reset via the trc register. 2.1 initialization and configuration the pb (and mc) contain a configuration space that uses the same access mechanism as described in the pci bus specification. with the exception of address decoding for bios accesses, the pb does not respond to host- initiated memory accesses until the associated registers are initialized. the device number for the pb is hardwired to 11001 for the 82454kx. in dual pb systems, during a hard reset (via a power-on hard reset or by programming the compatibility pbs trc register), both pbs set their internal configuration registers to predetermined default conditions. for dual pb systems, there are two pb configurations (compatibility and auxiliary pb). these configurations are defined by values on the iognt# and ioreq# signal lines (high or low voltage levels) on the rising edge of pwrgd. the values on iognt# and ioreq# define the pb identification (pbid) and are reported in the dbnum register (offset 49h). physical connections for the iognt# and ioreq# signals are shown in the section 3.5. the pbid value defines the lower two bits of the five-bit device number.
preliminary 27 a 82454kx/gx (pb) the bridge that is in the path to the boot rom is always the pb with device number=11001, and is referred to as the compatibility pb. the compatibility pb always decodes bios addresses after power-on reset. note: when the address decode ranges of the 450kx/gx devices are being updated, no other host bus traffic is allowed. this means that the code that updates initial configuration must be non-cached (to prevent speculative reads). further, in a multiprocessor system, precautions should be taken to assure that only one cpu is accessing configuration space at a time. 2.2 i/o space registers the pb has three registers located in i/o spacethe configuration address (confadd) register, the turbo and reset control (trc) register, and the configuration data (confdata) register. the confadd and confdata registers provide a window into the pbs configuration space registers (see section 2.3 for additional details). a specific pci bus, device, and register are selected by writing to the confadd register. data is read from or written to the selected register by accessing the confdata register. note that the confadd register is only selected by dword accesses to cf8h. this allows the confadd register to overlap other byte registers (e.g., the trc register at cf9h). the confdata register is not selected unless configuration accesses are enabled in the confadd register. this allows the confdata register to overlap other registers as well. table 7. i/o space registers i/o address mnemonic register name access cf8h confadd configuration address r/w cf9h trc turbo and reset control (compatibility pb only) r/w cfch confdata configuration data r/w note that in a dual pb system (82454gx only), the trc register is only in the compatibility pb and the auxiliary pb ignores this address.
28 preliminary 82454kx/gx (pb) a 2.2.1 confadd?configuration address register address offset: 0cf8h (dword access only) default: 00000000h attribute: read/write the confadd register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. for example, a write of 8000c8b8h to the confadd register can be used to access the 82453kx smm range register. bits description 31 configuration enable (cse). 1=enable. 0=disable. 30:24 reserved. 23:16 bus number (busnum). this field selects 1 of 255 possible buses in a system. when busnum=00h, the target of the configuration cycle is a host bus device or the pci bus directly connected to the pb (compatibility pb in an 450GX system), depending on the device number field. the bus number for the pci bus directly connected to a pb is programmed into the pbnum register (offset 4ah). if the pb (or mc) is not the target (devnum 15) and the bus number matches the number in the pbs pbnum register, a type 0 configuration cycle is generated on the pci bus. if the bus number is to a hierarchical pci bus below the pbs pci bus (busnum is between the values programmed into the pci bus number register and the subordinate pci bus number register), a type 1 configuration cycle is generated on the pci bus with the bus number mapped to ad[23:16] during the address phase. 15:11 device number (devnum). this field selects either an agent on the host bus (busnum=00h and devnum 3 16) or an agent on the pci bus selected by the bus number field. for the 82454kx, the pb device number is hardwired to 11001. this number is reported in the bdnum register. a device on the host bus has a device number greater than 16. note that logically a pb can support up to 16 physical devices on the pci bus connected directly to it. thus, when busnum=00h and devnum 15, a type 0 or type 1 configuration cycle is generated by the compatibility pb. during a type 0 configuration cycle, this field is decoded and one of ad[31:16] is driven to a 1. for device number n (0 n 15), ad[16+n] is driven to a 1. during a type 1 configuration cycle, this field is mapped to ad[15:11]. in an 82454gx dual pb system, the device number for each pb is determined at power-up and is reported in the bdnum register (offset 49h). the pb device number is always equal to or greater than 16.
preliminary 29 a 82454kx/gx (pb) 2.2.2 trc?turbo and reset control address offset: cf9h default: 00h attribute: read/write this register enables/disables bist, provides software generation of hard and soft resets, and enables/disables deturbo mode. 10:8 function number (funcnum). this field is mapped to ad[10:8] during pci configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the pb responds to configuration cycles with a function number of 000b; all other function number values attempting access to the pb (busnum=00h and devnum matching pb device number) generate a type 0 configuration cycle on the pci bus with no idsel asserted, which results in a master abort. 7:2 register number (regnum). this field selects one 32-bit register within a particular bus, device, and function as specified by the other fields in the confadd register. this field is mapped to ad[7:2] during pci configuration cycles. 1:0 reserved. bits description 7:4 reserved. 3 cpu bist enable. 1=enable. 0=disable. when enabled, the pb invokes cpu bist when the cpu is reset (the value of this bit overrides the value of the cpu hard reset bit). subsequent initiation of hard reset (through bit 2 of this register) causes the pb to perform a hard cpu reset, leaving init# asserted when reset# is released initiating cpu bist. 2 reset cpu. 1=hard reset, soft reset, or hard reset with bist (type is controlled by bits[3,1] of this register). the transition from 0 to 1 of this bit triggers the pb to initiate the cpu reset. therefore, bits[3,1] should be programmed before this bit is set. in addition, bit 0 must be 0 before programming this register. 1 hard reset enable. 1=hard reset. 0=soft reset. reset occurs when the reset cpu bit transitions from 0 to 1. 0 deturbo enable. 1=enable. 0=disable. note that this bit must be set to 0 before setting bit 2 to 1. bits description for the 82454gx in a dual pb system, this register is only available in the compatibility pb and is not part of the auxiliary pb.
30 preliminary 82454kx/gx (pb) a 2.2.3 confdata?configuration data register address offset: 0cfch default: 00000000h attribute: read/write confdata is a 32-bit read/write window into configuration space. the 32-bit portion of configuration space that is referenced by confdata is determined by the contents of confadd. the byte enables during the 0cfch access select which bytes of the 32-bit window are updated. 2.3 pci configuration space the pb fully supports mechanism #1 for host accesses to pci configuration space registers (refer to the pci specification for details on mechanism 1). the pb can perform three types of configuration cycles. 1. an internal access is performed if the bus number is 0, and the device number selects this pb. no pci cycles are generated. 2. a type 0 translation is performed if the pci device being configured is on this pbs pci bus (the bus number matches the number in the pbs pci bus number register), and the device number is less than or equal to 15. 3. a type 1 translation is performed if the device being configured is on another hierarchical pci bus below the pbs pci bus (the bus number is between the pbs pci bus number and subordinate pci bus number). the pci configuration space protocol requires that all pci buses in a system be assigned a bus number. furthermore, bus numbers must be assigned in ascending order within hierarchical buses. each bridge must have a register that contains its pci bus number and a register that contains its subordinate pci bus number. the pci bus number and subordinate pci bus number must be loaded by post code. the subordinate pci bus number is the bus number of the last hierarchical pci bus under the current bridge. (the pci bus number and subordinate pci bus number are the same in the last hierarchical bridge.) at the top of the hierarchy, peer bridges continue the ascending bus numbering scheme. refer to the pci specification for additional examples. for the 450kx/gx, the implementation of the pci configuration protocol logically maps the configuration registers of the pb (and mc) to bus number 0. these devices, which are on the host bus, use device numbers 16 through 30 (figure 2). device numbers below 15 can be used on the pci bus that uses bus number 0. this allows a system to be designed with hierarchical pci buses starting with bus number 0. all bridges have programmable pci bus numbers and programmable subordinate pci bus numbers as described in the pci cse protocol for dual pci bridge systems. a pbs bus number register should be programmed to the number of the pci bus immediately beneath it. however, the pbs configuration registers remain at bus number 0. the pb is the response agent for cpu accesses to the confadd location. the mc snoops writes to this location. the device selected by the confadd register responds to confdata accesses. bits description 31:0 configuration data window. if bit 31 of confadd=1, an access to confdata i/o space is mapped to configuration space using the contents of confadd. for the 82454gx, the compatibility pb is the response agent for cpu accesses to the confadd location and the auxiliary pb as well as the mcs snoop writes to this location.
preliminary 31 a 82454kx/gx (pb) the pb (both pbs in an 82454gx dual pb system) defaults to a pci bus number equal to 0 after power-on reset. the mc is hard coded to bus number 0. note that the 82454 does not support programmable special cycles of the pci specification 2.0. figure 2. bus number assignments . table 8. device numbers for bus number 0 device unique id loaded at reset pci device number host bus agent id cpu n/a 0000C0111 mc 00 10100 na mc 01 10101 na pb 01 11001 1001 pb 10 11010 1010 reserved all others all others all others for the 450GX, each pb and mc must have a unique id assigned at power-on reset (via strapping options). the relation between the pb and mc number, the device number, and the host bus agent number is shown in table 8. the pbid is also used as the pb agent id when it is a host bus master. busnum=0 (devnum 3 16) busnum=0 busnum=(x+1) cpu mc busnum=1 busnum=x busnum=(x+2) busnum=y pci-pci bridge pci-pci bridge pci-pci bridge pci-pci bridge (devnum 15) compatibility pb auxiliary pb x, and y can be any number subject to: y>x, and y 255.
32 preliminary 82454kx/gx (pb) a 2.4 pb pci configuration registers table 9. pci configuration space registers address offset mnemonic register name access 00C01h vid vendor identification ro 02C03h did device identification ro 04C05h pcicmd pci command r/w 06C07h pcists pci status ro, r/wc 08h rid revision identification ro 09C0bh classc class code ro 0ch clsize pci cache line size ro 0dh pltmr pci latency timer r/w 0e headt header type ro 0f bist bist register r/w 10C3fh reserved 40C43h tsm top of system memory r/w 44C47h reserved 48h pdm pci decode mode r/w 49h bdnum bridge device number ro 4ah pbnum pci bus number r/w 4bh psbnum pci subordinate bus number r/w 4c pbc pb configuration r/w 4dC50h reserved 51h dcc deturbo counter control r/w 52h reserved 53h crwc cpu read/write control r/w 54C55h prwc pci read/write control r/w 56h reserved 57h smme smm enable r/w 58h vbae video buffer area enable r/w 59C5fh pam[0:6] programmable attribute map (7 registers) r/w 60C6fh reserved 70h errcmd error reporting command r/w 71h errsts error reporting status r/wc
preliminary 33 a 82454kx/gx (pb) 72C77h reserved 78C79h mgr memory gap range r/w 7aC7b mgua memory gap upper address r/w 7cC7fh pfb pci frame buffer r/w 80C87h reserved 88C8bh hmgsa high memory gap start address r/w 8cC8fh hmgea high memory gap end address r/w 90C97h reserved 98C9bh reserved (450kx) iosr1 i/o space range #1 (450GX) r/w 9c pcirsr pci reset r/w 9dC9fh reserved a0Ca3h reserved (450kx) iosr2 i/o space range #2 (450GX) r/w a4hCa7h apicr i/o apic range r/w a8Cafh reserved b0Cb1h confvr configuration values driven on reset r/w b2Cb3h reserved b4Cb5h csconfv captured system configuration values ro b6Cb7h reserved b8Cbbh smmr smm range r/w bc hbiosr high bios register r/w bdCbfh reserved c0Cc3h exerrcmd pb extended error reporting command r/w c4Cc7h exerrsts pb extended error reporting status r/wc c8Ccbh pbrtmr pb retry timers r/w ccCffh reserved table 9. pci configuration space registers (continued) address offset mnemonic register name access
34 preliminary 82454kx/gx (pb) a 2.4.1 vid?vendor identification register address offset: 00C01h default: 8086h attribute: read only the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. writes to this register have no affect. 2.4.2 diddevice identification register address offset: 02C03h default: 84c4h attribute: read only this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no affect. 2.4.3 pcicmdpci command register address offset: 04C05h default: 0007h attribute: read/write this register controls the pbs ability to respond to pci cycles. see pcists register for corresponding error reporting. see errcmd register (70h) for additional controls. bits description 15:00 vendor identification. this is a16-bit value (8086) assigned to intel. bits description 15:00 device identification. this is a16-bit value (84c4) assigned to the pb. bits description 15:9 reserved. 8 serr# enable. 1=enable. 0=disable. when enabled, the pb asserts serr#, if the corresponding bits in the errcmd register are enabled. 7 wait cycle control. (not implemented). this bit is hardwired to 0. 6 parity error response enable. 1=enable pci parity error checking (see errcmd register for generation of perr# signal.). 0=disable. note that pci parity errors will not be reported using serr# unless both this bit and bit 8 are set to 1. 5 reserved. 4 memory write and invalidate enable. 1=enable. 0=disable. when disabled, memory write commands are used. 3 reserved.
preliminary 35 a 82454kx/gx (pb) 2.4.4 pcists?pci status register address offset: 06C07h default: 0240h attribute: read only and read/write clear the pcists register reports the occurrence of a pci master abort/pci target abort, system error, and parity errors. this register also indicates the devsel# timing that has been set by the pb hardware. software sets the bits labeled r/wc to 0 by writing a 1 to them. 2 bus master enablero. the pb does not support disabling its bus master capability. this bit is hardwired to 1. 1 memory space enable. 1=enable pci memory accesses to the host bus. 0=disable. 0 i/o space enable. 1=enable pci i/o accesses to the host bus. 0=disable. bits description 15 parity error detectedr/wc. 1=pb detected a pci address or data parity error. the pb checks all address cycles, regardless of the intended target, for address parity errors. when the pb is involved in a pci transaction (as either master or target), it checks all data cycles for data parity errors. the parity error detected bit is set independent of whether parity error reporting (bit 6 in the pcicmd register) is enabled. 14 signaled system errorr/wc. 1=pb asserted the serr# signal. 13 received master abortr/wc. 1=pb is pci bus master and terminates its transaction (other than special cycle commands) with a master-abort. 12 received target abortr/wc. 1=pb as a pci bus master received a target abort. 11 signaled target abortr/wc. 1=pb issued a target abort. this only happens for invalid byte enables during an i/o access or a hard failure from a host bus agent. 10:9 devsel# assertionro. bits[10:9]=01 (indicates medium timing when the pb responds as a target). 8 data parity error reportedr/wc. this bit is set to 1 when all of the following conditions are met: 1.) the pb asserted perr# or sampled perr# asserted. 2.) the pb was the bus master for the transaction in which the error occurred. 3.) the parity error response bit is set to 1 in the pcicmd register. 7 fast back-to-back capablero. this bit is hardwired to 0 to indicate that the pb is not capable of accepting fast back-to-back transactions that are not to the same agent. 6:0 reserved. bits description
36 preliminary 82454kx/gx (pb) a 2.4.5 rid?revision identification register address offset: 08h default: see stepping information in the 450 gx/kx specification update attribute: read only this register contains the revision number of the pb. 2.4.6 classcclass code register address offset: 09C0bh default: 060000h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the pb. this register also identifies the base class code and the function sub-class in relation to the base class code. 2.4.7 clsizecache line size register address offset: 0ch default: 08h attribute: read only this register indicates the system cache line size. the value equals the number of 32-bit dwords in the cache line. bits description 7:0 revision identification value. this is an 8-bit value that indicates the revision identification number for the pb. bits description 23:16 base class code (bcc). 06h=bridge device. 15:8 sub-class code (scc). 00h=host bridge. 7:0 programming interface (pi). 00h=hardwired as a host-to-pci bridge. bits description 7:0 system cache line size. 08h=32 byte cache line size.
preliminary 37 a 82454kx/gx (pb) 2.4.8 pltmr?pci latency timer address offset: 0dh default: 20h attribute: read/write this register controls the duration of a burst cycle. 2.4.9 headtheader type register address offset: 0eh default: 00h attribute: read only this register indicates the header type for the pb. 2.4.10 bistbist register address offset: 0fh default: 00h attribute: read/write the built-in self test (bist) function is not supported by the pb. writes to this register have no effect. bits description 7:0 pci master latency timer value. if pgnt# is negated during a pb initiated pci burst cycle, the pb limits the duration of the burst cycle to the number of pci clocks specified in this field. masters capable of bursting multiple lines perform better with a higher value than the default. a value of 40h, for example, will allow a bursting master to always transfer at least four cache lines before a disconnect occurs. bits description 7:0 header type (htype). 00h=basic configuration space format. bits description 7 bist supported. this read only bit is set to 0 indicating that the 82454 does not support bist. 6 start bist. this function is not supported. 5:4 reserved. 3:0 completion code. this read only field returns 0 when read.
38 preliminary 82454kx/gx (pb) a 2.4.11 tsm?top of system memory register address offset: 40C43h default: 0000h attribute: read/write this register permits the pb to respond to memory transactions above the main memory range of the mc(s) on the host bus. 2.4.12 pdmpci decode mode address offset: 48h default: 06h attribute: read/write this register masks ad[31:16] for host i/o transactions. in addition, this register enables/disables isa aliasing for i/o addresses in the range 100C3ffh. note that the pb never forwards pci i/o addresses above 64 kbytes to the host bus. bits description 31 host bus top of main memory default enable. 1=enable. 0=disable. when enabled, the pb forwards all host bus memory space transactions between the top of memory (determined by bits [15:0] of this register) and 64 gbytes to the pci bus, except regions defined by the memory gap registers (mgr/mgua and hmgsa/hmgea registers). when disabled, the pb ignores these transactions. note that when memory accesses are enabled to be forwarded from the host bus to pci, the pb blocks (ignores the transaction) the corresponding memory accesses initiated on the pci bus from being forwarded to the host bus. 30:16 reserved. must be programmed to 0s when writing this register. 15:0 top of host bus system memory address. bits[15:0] of this register are compared to a[35:20]. the top of system memory is programmed in units of 1 mbyte (i.e., 00001h=1 mbyte, 00002h= 2 mbytes, 00003=3 mbytes, etc.). bits description 7:3 reserved. 2 i/o address mask enable. 1=enable (default). 0=disable. when enabled, the pb forces pci ad[31:16] to zero for host bus to pci i/o transactions. (the processor may assert a16 during i/o in real mode.) in all cases, the pb only decodes the lower 64 kbytes of the host bus i/o address. 1 i/o aliasing enable. 1=enable isa expansion aliasing (default). 0=disable. aliasing algorithm (bit 1=1) if a[9:8]=00, the address does not fall into an i/o alias range and a[15:4] are compared to the i/o space ranges defined by the iosr1 and iosr2 registers (offsets 98C9bh and a0Ca3h, respec- tively). if a[9:8] 1 00h, the address is in an alias range so a[15:10] are masked (the address is aliased for decoding purposes) before comparing the address to the i/o space range registers. note that, when i/o aliasing is enabled (bit 1=1) and the i/o address mask enable feature is disabled (bit 2=0), the pb decoder aliases any bus i/o address above 64 kbytes. in an 82454gx dual pb system, both pbs must have this bit set the same. otherwise, both pbs may respond to host bus transactions targeting an aliased isa expansion i/o address. 0 reserved.
preliminary 39 a 82454kx/gx (pb) 2.4.13 bdnum?bridge device number register address offset: 49h default: 0001 1001h (82454kx) attribute: read only this register contains the bridge device number. for the 82454kx this value is hardwired to 11001. . 2.4.14 pbnumpci bus number register address offset: 4ah default: 00h attribute: read/write this register contains the bus number of the pci bus that is immediately behind the pb. note, this does not affect the bus number for the pb configuration registers. the pb configuration registers are always addressed as bus number 0. bits description 7:5 reserved. 4:2 fixed value. the upper three bits of the pb bridge device number are always 110. 1:0 82454kx: fixed value. the lower two bits of the pb bridge device number are always 01 82454gx: pb identification (pbid). the lower two bits of the bridge device number encoding is defined as follows: bits[1:0] function 0 0 reserved. 0 1 used by the compatibility pb. 1 0 used by the auxiliary pb in a two pb system. 1 1 reserved. bits description 7:0 bus number. the pci bus number of the pci bus immediately behind the pb. 0001 1001h (compatibility 82454gx) 0001 1010h (auxiliary 82454gx) for the 82454gx, this number is loaded from the iognt# and ioreq# pins during power-up. only the compatibility pb (pbid = 01) responds to initial bios code fetches (defaults to this area enabled). for the 82454gx, both pbs default to bus number 0. the auxiliary pb must be changed before configuration accesses are made to the pci bus.
40 preliminary 82454kx/gx (pb) a 2.4.15 psbnum?subordinate bus number register address offset: 4bh default: 00h attribute: read/write this register contains the bus number of the last hierarchical bridge under the current bridge. 2.4.16 pbcpb configuration register address offset: 4ch default: 39h (82454kx) attribute: read/write this register configures the pb for various operations. bits description 7:0 last bus number. the bus number of the last hierarchical bridge under the current bridge. bits description 7 long watchdog timer enable (lwte). 1=30 ms. 0=1.5 ms 6 lock atomic reads. 1=reads that cross a pci dword boundary are issued as locked reads. this bit must be enabled for systems containing a pci to pci bridge. 5 reserved. 4 branch trace message response enable. 1=pb responds to the branch trace message host bus command. (default). used by external development tools that need to capture the processor branch trace message. 0=pb ignores this command. 3 init on shutdown enable. 1=pb asserts the init# signal when receiving a shutdown command. (default). 2 reserved. for the 82454gx, both pbs default to subordinate bus number 0. the auxiliary pb must be changed before configuration accesses are made to the pci bus. 39h (compatibility pb) 3ah (auxiliary pb) in a 450GX dual pb system, the auxiliary bridge ignores this bit. for the 82454gx in a dual pb system, this bit is only used in the compatibility pb and is not used in the auxiliary pb.
preliminary 41 a 82454kx/gx (pb) 2.4.17 dcc?deturbo counter register address offset: 51h default: 80h attribute: read/write in deturbo mode this register determines how many clocks bpri# is asserted in order to throttle the host bus. the host bus pipeline is stalled at a rate determined by this register. the deturbo counter value is compared to an 8 bit counter running at the host bus clock (bclk) divided by 8. 2.4.18 crwccpu read/write control register address offset: 53h default: 00h attribute: read/write this register enables/disables processor writes to pci to be posted in the pb. 1:0 82454kx: reserved. must be set to 01. bits description 7:0 deturbo count value. when the counter value is greater than this register value, bpri# is asserted by the pb. bpri# is negated when the count value is less than or equal to this register value. smaller values in this register result in slower deturbo emulation speeds. bits description 7:2 reserved. 1 host-to-pci write (outbound) posting enable. 1=enable. 0=disable. 0 reserved. bits description 82454gx: bridge arbitration mode. these bits determine the arbitration mode the pb uses before taking ownership of the processor bpri# signal. bits[1:0] function 00 no arbitration (single bridge system) 01 arbitration mode (this pb provides the arbitration unit for an auxiliary pb) 10 external arbiter mode. (this setting is for the auxiliary bridge) 11 reserved. note that, in a single pb system where the internal arbiter is not needed, this field should be changed from its default value to 00. for the 82454gx in a dual pb system, this register is only available in the compatibility pb and is not available in the auxiliary pb.
42 preliminary 82454kx/gx (pb) a 2.4.19 prwc?pci read/write control address offset: 54C55h default: 00h attribute: read/write the prwc register enables/disables read pre-fetching on the host bus. this register also enables/disables the assembly of back-to-back sequential host-to-pci memory space cache line writes into pci burst cycles and enables/disables pci-to-host (inbound) write posting. bits description 15:10 reserved. 9 cpu line read pre-fetch for pci memory read commands enable. 1=enable. 0=disable. when enabled, pci memory read commands cause a fetch of a cpu cache line plus a pre-fetch of three or more cpu cache lines (pre-fetching does not cross 4 kbyte address boundaries). this bit has no affect unless cpu line read enable (bit 8) is also set. 8 cpu line read for pci memory read commands enable. 1=enable. 0=disable. this bit is set to enable pci memory read commands to fetch full cpu cache lines. when disabled, a pci memory read command results in read partials on the host bus. 7 reserved. 6 cpu line read multiple pre-fetch for pci memory read multiple commands enable. 1=enable. 0=disable. when enabled, pci memory read multiple commands cause a fetch of a cpu cache line plus a pre-fetch of three or more cpu cache lines (pre-fetching does not cross 4 kbyte address boundaries). this bit has no affect unless cpu line read multiple enable (bit 5) is also set. 5 cpu line read multiple for pci memory read multiple commands enable. 1=enable. 0=disable. when enabled, pci memory read multiple commands fetch full cpu cache lines. when disabled, a pci memory read multiple command results in read partials on the host bus. 4 cpu line read pre-fetch for pci memory read line commands enable. 1=enable. 0=disable. when enabled, pci memory read line commands cause a fetch of a cpu cache line plus a pre-fetch of three or more full cpu cache lines. pre-fetching does not cross 4 kbyte address boundaries. this bit has no affect unless cpu line read enable (bit 3) is also set. 3 cpu line read for pci memory read line commands enable. 1=enable. 0=disable. when enabled, pci memory read line commands fetch full cpu cache lines. when disabled, a pci memory read line command results in read partials on the host bus. 2 reserved. 1 burst write assembly enable. 1=enable. 0=disable. when enabled, back-to-back sequential cpu-to-pci memory space cache line writes (uswc memory type) are converted to continuous pci write bursts (write combining). this feature should only be enabled if the cache line writes are guaranteed not to cross component address boundaries. 0 pci-to-host bus write (inbound) posting enable. 1=enable. 0=disable. (caution: do not enable if cpu to pci locks split across component boundaries on the host bus.)
preliminary 43 a 82454kx/gx (pb) 2.4.20 smme?smram enable register address offset: 57h default: 00h attribute: read/write this register enables the address range programmed into the smmr register (b8Cbbh) and permits system management mode (smm) ram to overlay memory space normally mapped to the pci bus. 2.4.21 vbaevideo buffer area enable register address offset: 58h default: 02h (82454kx) attribute: read/write the vbae register selects where vga buffer requests are directed. this register defaults to read/write accesses directed to the pb (compatibility pb only for the 82454gx). the mc and auxiliary pb (82454gx only) default to this range disabled. bits description 7:4 reserved. 3 smm ram normal decode range override enable. 1=enable. 0=disable. when enabled,. the pb ignores the smm ram gap range for all transactions and uses normal decode ranges (i.e., the smmr register has no affect on pb address decoding). when disabled, accesses to the smm range made when smmem# is asserted are ignored by the pb, even if the address is within the positive decode range of a different range register in the pb. accesses outside of the smm range are not affected by the state of the smmem# signal. smm ram may overlay memory space normally mapped to the pci bus. 2:0 reserved. bits description 7:2 reserved. 1 video buffer area enable (a0000Cbffffh). 1 = host bus requests to the vga buffer range are forwarded to the pci bus. 0=host bus requests to the vga buffer range are ignored. 0 reserved. 02h (compatibility pb), 00h (auxiliary pb)
44 preliminary 82454kx/gx (pb) a 2.4.22 pam[0:6]?programmable attribute map register address offset: pam0 (59h)pam6 (5fh) default: pam030h; pam[1:6]33h (82454kx) read/write these seven registers select read only (re=1, we=0), write only (re=0, we=1), or read/write (re=1, we=1) access attributes for 14 memory regions between the 512 kbyte and 1 mbyte address range. the individual memory regions can also be disabled (re=0, we=0). each register controls two regions; bits [7:4] control one region and bits [3:0] control the other region. note that the default for the system bios region is read/write enabled. the default for all other regions is read/write disabled. when a region is enabled, the corresponding host bus access is forwarded to pci; the corresponding pci access is ignored (not forwarded to the host bus). when a region is disabled, the corresponding host bus access is ignored (not forwarded to the pci bus); the corresponding pci access is forwarded to the host bus. note that the mc has corresponding pam registers. only one device (mc/pb) should have the same space enabled at one time to avoid access conflicts. pam attribute bits memory segment comments offset register 7,3 6,2 5,1 4,0 pam0[7:4] reserved we re 0f0000C0fffffh bios 59h pam0[3:0] reserved we re 080000C09ffffh 512C640 kb 59h pam1[7:4] reserved we re 0c4000C0c7fffh isa expansion 5ah pam1[3:0] reserved we re 0c0000C0c3fffh isa expansion 5ah pam2[7:4] reserved we re 0cc000C0cffffh isa expansion 5bh pam2[3:0] reserved we re 0c8000C0cbfffh isa expansion 5bh pam3[7:4] reserved we re 0d4000C0d7fffh isa expansion 5ch pam3[3:0] reserved we re 0d0000C0d3fffh isa expansion 5ch pam4[7:4] reserved we re 0dc000C0dffffh isa expansion 5dh pam4[3:0] reserved we re 0d8000C0dbfffh isa expansion 5dh pam5[7:4] reserved we re 0e4000C0e7fffh bios extension 5eh pam5[3:0] reserved we re 0e0000C0e3fffh bios extension 5eh pam6[7:4] reserved we re 0ec000Ceffffh bios extension 5fh pam6[3:0] reserved we re 0e8000C0ebfffh bios extension 5fh pam030h (compatibility pb), 00h (auxiliary pb) pam[1:6]33h (compatibility pb), 00h (auxiliary pb) for the 450GX, the default for the system bios region in the compatibility pb is read/write enabled. the default for the auxiliary pb is read/write disabled.
preliminary 45 a 82454kx/gx (pb) 2.4.23 errcmd?error reporting command register address offset: 70h default: 00h attribute: read/write this register provides control for generating pci serr# and perr# error signals. note that for bits[7:4], serr# must be enabled in the pcicmd register. for bit 3, pci parity error checking must be enabled in the pcicmd register. 2.4.24 errstserror reporting status register address offset: 71h default: 00h attribute: read/write clear this register reports certain pci data and address parity errors and for detection of a cpu shutdown cycle. software sets these bits to 0 by writing a 1 to them. bits description 7 serr# on receiving target abort (pb is pci bus master). 1=enable. 0=disable. 6 serr# on transmitted data parity error (detected via perr#). 1=enable. 0=disable. 5 serr# on received data parity error (detected via par). 1=enable. 0=disable. the pb is the master. 4 serr# on address parity error enable. 1=enable. 0=disable. 3 perr# on data parity error enable. 1=enable. 0=disable. the received data can be the result of a pb read or another pci master write to the pb. 2:0 reserved. bits description 7 reserved. 6 pci data parity error when writing pci data (perr# was asserted). 1=detected parity error. 5 data parity error when reading pci data (par was incorrect). 1=detected parity error. 4 detected pci address parity error. 1=par was incorrect when receiving address and c/be[3:0]# from another pci master. 3:1 reserved. 0 shutdown cycle from host bus detected. 1=detected. the pb optionally asserts init# as per the setting in the pbc register (4ch). for the 82454gx in a dual pb system, this bit is only used in the compatibility pb and is not used in the auxiliary pb.
46 preliminary 82454kx/gx (pb) a 2.4.25 mgr?memory gap range register address offset: 78C79h default: 00h attribute: read/write this register is used with the mgua register (7aC7bh) to define the memory gap range. when enabled, the corresponding host bus access is forwarded to pci; the corresponding pci access is ignored (not forwarded to the host bus). when disabled, the corresponding host bus access is ignored (not forwarded to the pci bus); the corresponding pci access is forwarded to the host bus. 2.4.26 mguamemory gap upper address register address offset: 7aC7bh default: 00h attribute: read/write this register is used with the mg register (78C79h) to define the memory gap range. bits description 15 memory space gap enable. 1=enable. 0=disable. 14:1 0 memory gap size. this field defines the memory gap size as follows: bits[14:10] size bits[14:10] size 00000 1 mb 11100 8 mb 00100 2 mb 11110 16 mb 01100 4 mb 11111 32 mb note that all other combinations are reserved. 9:8 reserved. 7:4 gap starting address. these bits correspond to address bits a[23:20]. the remaining address bits are specified in the mgua register. when bits[7:4]=0000, this memory gap is disabled. 3:0 reserved. bits description 15:12 reserved. should be set to 0. 11:0 memory gap range upper address. these bits correspond to the memory space gap starting address bits a[35:24].
preliminary 47 a 82454kx/gx (pb) 2.4.27 pfb?pci frame buffer register address offset: 7cC7fh default: 00h attribute: read/write this register defines a pci frame buffer range. when enabled, the corresponding host bus access is forwarded to pci; the corresponding pci access is ignored (not forwarded to the host bus). when disabled, the corresponding host bus access is ignored (not forwarded to the pci bus); the corresponding pci access is forwarded to the host bus. bits description 31:20 frame buffer starting address. these bits correspond to address bits a[31:20] and select the starting address in 1 mbyte increments. all 0s=disable range (overrides bit 11). 19:13 reserved. 12 vga performance mode enable. 1=enable. 0=disable. when enabled, the vga memory range of a0000Cbffffh uses the same features that are enabled for the frame buffer address range (i.e., disable locks). 11 frame buffer range enable. 1=enable. 0=disable. this bit does not affect the vga memory range defined by the vbae register (offset 58h). 10 reserved. 9 frame buffer lock disable. 1=disable. 0=enable. when locks are disabled, cpu locked requests (i.e., exchange instructions) do not result in a pci exclusive access. note that, locking is usually not necessary when accessing frame buffer data. 8 reserved. 7 flush inbound data buffer on non-deferred frame buffer reads. 1=do not flush. 0=flush. 6:5 reserved. 4:0 frame buffer size. this field defines the frame buffer size as follows: bits[14:10] size bits[14:10] size 00000 1 mb 00111 8 mb 00001 2 mb 01111 16 mb 00011 4 mb 11111 32 mb note that all other combinations are reserved.
48 preliminary 82454kx/gx (pb) a 2.4.28 hmgsa?high memory gap range start address register address offset: 88C8bh default: 00h attribute: read/write this register is used with the hmgea register (8cC8f) to define the high memory gap. when enabled, the corresponding host bus access is forwarded to pci; the corresponding pci access is ignored (not forwarded to the host bus). when disabled, the corresponding host bus access is ignored (not forwarded to the pci bus); the corresponding pci access is forwarded to the host bus. 2.4.29 hmgeahigh memory gap end address register address offset: 8cC8fh default: 00h attribute: read/write this register is used with the hmgsa register (88C8bh) to define the high memory gap. bits description 31 high memory gap enable. 1=enable. 0=disable. 30:16 reserved. these bits should be set to 0. 15:0 high memory gap start address. these bits correspond to address bits a[35:20] and select the starting address in 1 mbyte increments. all 0s=disable range. bits description 31:16 reserved. these bits should be set to 0. 15:0 high memory gap end address. these bits correspond to address bits a[35:20] and select the ending address in 1 mb increments.
preliminary 49 a 82454kx/gx (pb) 2.4.30 iosr1?i/o space range 1 register (82454gx only) 2.4.31 pcirsr?pci reset register address offset: 9ch default: 00h attribute: read/write this register permits software to reset the pci bus without also resetting the cpu bus. note, the pci bus is always reset when the host bus is reset through a hard or power-on reset. bits description 31:20 i/o space range 1 end address. bits [31:20] correspond to a[15:4]. must be set to the same value in both bridges. 19:16 reserved. 15:4 i/o space range 1 start address. bits [15:4] correspond to a[15:4]. must be set to the same value in both bridges. 3:1 reserved. 0 i/o space range 1 enable. 1=forward host bus accesses in the range to pci and ignore pci bus accesses in the range. 0=ignore host bus accesses in the range and forward pci bus accesses in the range to the host bus. compatibility bridge: 1=default. to open a gap in the compatibility bridge i/o space, this bit must set to 0. auxiliary bridge: 0=default. to claim an i/o range in the auxiliary bridge, this bit must be set to 1. bits description 7:1 reserved. 0 reset pci bus. setting this bit from 0 to 1 causes the pb to assert pcirst# for at least one milli- second. resetting the pci bus could cause unwanted system signals to drive into the processor. be sure to understand the state of any signals going from the pci bus back to the processor during reset. see section 3.7.5. address offset: 98C9bh default: fff0 0001h (compatibility pb) fff0 0000h (auxiliary pb) attribute: read/write this register defines an i/o space range. a second i/o space range is defined by the iosr2 register. except for the ranges defined by these two registers, the compatibility pb forwards all host bus accesses to pci (and ignores pci bus accesses) and the auxiliary pb ignores all host bus accesses (and forwards pci bus accesses to the host bus).
50 preliminary 82454kx/gx (pb) a 2.4.32 iosr2?i/o space range 2 register (82454gx only) . 2.4.33 apicri/o apic range register address offset: a4Ca7h default: 00fe c001h (82454kx) attribute: read/write this range defines an i/o apic range. there can be up to 16 apics, with contiguous ascending unit ids below a pb. one of the 16 apic 4 kbyte blocks must be reserved for all cpu local apic units. (multiple cpu(s) may use the same local apic address since local apic transactions are not visible on the host bus.) the pb responds to i/o apic address range (base + x000h) through (base + yfffh) where x is the i/o apic starting unit id and y is the highest unit id number. note that a 64 kbyte range is allocated to apic space. local apic transactions are not visible on the host bus, but still require uc mtrr attributes. the local apic base address register in each processor should be programmed to point to one of the 4 kbyte blocks in the 64 kbyte apic range so that one mtrr may be used for local and i/o apic configuration ranges. the mc does not reclaim any 64 kbyte memory gaps created for the apic range. bits description 31:20 i/o space range 2 end address. bits[31:20] correspond to a[15:4]. must be set to the same value in both bridges. 19:16 reserved. 15:4 i/o space range 2 start address. bits[15:4] correspond to a[15:4]. must be set to the same value in both bridges. 3:1 reserved. 0 i/o range 2 enable. 1=forward host bus accesses in the range to pci and ignore pci bus accesses in the range. 0=ignore host bus accesses in the range and forward pci bus accesses in the range to the host bus. compatibility bridge: 1=default. to open a gap in the compatibility bridge i/o space, this bit must set to 0. auxiliary bridge: 0=default. to claim an i/o range in the auxiliary bridge, this bit must be set to 1. address offset: a0Ca3h default: fff0 0001h (compatibility pb) fff0 0000h (auxiliary pb) attribute: read/write this register defines an i/o space range. a second i/o space range is defined by the iosr1 register. except for the ranges defined by these two registers, the compatibility pb forwards all host bus accesses to pci (and ignores pci bus accesses) and the auxiliary pb ignores all host bus accesses (and forwards pci bus accesses to the host bus) 00fe c001h (compatibility pb) 00fe c000h (auxiliary pb) if there is an i/o apic behind more than one pb, each pb must use the same apic base address and all 64kb of apic range must be accounted for among the pbs.
preliminary 51 a 82454kx/gx (pb) 2.4.34 confvr?configuration values driven on reset register address offset: b0Cb1h default: 00h attribute: read/write during a programmed hard reset (via the pbs trc register), this register provides the processors and host bus agents with certain configuration details that have been programmed into the pb (compatibility pb only for the 82454gx). during a power-on reset, this register is set to its default values and these values are driven on the appropriate host bus signals. after initialization, software programs this register. during a programmed hard reset this register retains its programmed values and these values are driven on the host bus when the pb asserts reset#. bits description 31:28 reserved. must be set to zero. 27:12 i/o apic base address. bits[27:12] correspond to a[35:20] and select the i/o apic base address in 1 mb increments. 11:8 i/o apic starting unit id. this field contains the lowest unit id (0Cfh) of any apics located below this bridge. 7:4 highest unit id number. this field contains the highest unit id (0Cfh) of any apics located below this bridge. 3:1 reserved. 0 i/o apic range enable. 1=enable. 0=disable. bits description 15:13 reserved. 12:11 apic cluster id. software programs this field with the apic cluster id. the value in these bits are driven to the processors on a[12:11]#. 10 82454kx: reserved. 9 berr# input enable. 1=enable. 0=disable. this bit value is driven on a9#. all host bus agents enable berr# reporting if this bit is 1. see the exerrcmd register for additional signal details. 8 82454kx: reserved. for the 82454gx in a dual pb system, this register is only available in the compatibility pb and is not available in the auxiliary pb. 82454gx: binit# input enable. 1=enable. 0=disable. the value in this bit is driven on a10#. all host bus agents enable binit# if this bit is 1. see exerrcmd register for additional signal details. 82454gx: aerr# input enable. 1=enable. 0=disable. used to enable the reporting of address parity errors. the value in this bit is driven on a8#. all host bus agents cancel erroneous requests if this bit is 1. expected use is to enable this bit and then map aerr# to nmi in the exerrcmd register.
52 preliminary 82454kx/gx (pb) a 2.4.35 csconfv?captured system configuration values register address offset: b4Cb5h default: xxh (x=captured during hard reset) attribute: read only the register reports how the system is set up for certain functions. the values in this register are captured on the rising edge of reset#. 7 in-order queue depth 1 select. 1=depth of 8. 0=depth of 1. the value in this bit is driven on a7#. pentium pro processors use an in-order queue depth of 8 if this bit is 1. 6 1m power-on reset vector select. 1=1 mbyte. 0=4 gbyte. the value in this bit is driven on a6#. pentium pro processors use the 1 mbyte reset vector if this bit is 1. 5 frc mode enable. 1=enable. 0=disable. the value in this bit is driven on a5#. pentium pro processors enter frc enabled mode if this bit is 1. 4:0 reserved. bits description 15:13 reserved. 12:11 apic cluster id. the pb captures this value from a[12:11]#. 10 binit# input enable. 1=enable. 0=disable. the pb captures this value from a10#. 9 berr# input enable. 1=enable. 0=disable. the pb captures this value from a9#. 8 aerr# input enable. 1=enable. 0=disable. the pb captures this value from a8#. 7 in-order queue depth 1 select. 1=depth of 8. 0=depth of 1. the pb captures this value from a7#. see exerrcmd register for additional signal details. 6 1m power-on reset vector. 1=1 mbyte. 0=4 gbyte. the pb captures this value from a6#. 5 frc mode enable. 1=enable. 0=disable. the pb captures this value from a5#. 4:0 reserved. bits description for the 82454gx, see the exerrcmd register (offset c0Cc3h) for additional details. caution: programming the corresponding output enable bit in the exerrcmd register must be consistent with the value in this bit captured from the host bus. otherwise, incorrect system operations will result. for the 82454gx, see the exerrcmd register (offset c0Cc3h) for additional details. for the 82454gx, see the exerrcmd register (offset c0Cc3h) for additional details. caution: programming the corresponding output enable bit in the exerrcmd register must be consistent with the value in this bit captured from the host bus. otherwise, incorrect system operations will result.
preliminary 53 a 82454kx/gx (pb) 2.4.36 smmr?smram range register address offset: b8Cbbh default: 0000 0005h attribute: read/write the range programmed into this register is required when smram addresses overlap addresses normally mapped to the pci bus. 2.4.37 hbiosrhigh bios range register address offset: bch default: 01h (82454kx) attribute: read/write this register enables/disables the 0C512 kbyte and the high bios ranges. when enabled, the pb forwards host bus memory accesses in this range to pci and ignores pci memory accesses to the same range. when disabled, the pb ignores host bus memory accesses to this range and forwards pci memory accesses to the same range to the host bus. 2.4.38 exerrcmdpb extended error reporting command register address offset: c0Cc3h default: 0000 0010h attribute: read/write this register enables/disables the reporting of certain error conditions. bits description 31:28 smm range size. the size (in 64 kbyte increments) is selected as follows: bits[31:28] size bits[31:28] size 0000 64 kbyte 0011 256 kbytes 0001 128 kbytes . . . . . . 0010 192 kbytes 1111 1 mbytes 27:16 reserved. must be set to zero. 15:0 smm range start address. bits[15:0] correspond to a[31:17] and select the starting address in 64 kbyte increments beginning at 64 kbytes. the default starting address is a0000h and ranges to bffffh. bits description 7:5 reserved. 4 0C512 kbyte range enable. 1=enable. 0=disable. 3:1 reserved . 0 2 mbyte high bios range enable (00 ffe0 0000C00 ffff ffffh). 1=enable. 0=disable. 01h (compatibility pb) 00h (auxiliary pb)
54 preliminary 82454kx/gx (pb) a bits description 31:14 reserved. 13 report errors using hard fail/serr# enable. 1=enable (hard fail mechanism). 0=disable (pb uses serr#). these errors are reported when the pb is servicing a host bus request and detects an error. note that the pb does not report perr# through hard fail. 12 report pci master abort errors. 1=enable. 0=disable. when enabled, the pb normally returns all 1s to cpu read transactions that receive a master abort time-out. note that bit 13 in the pcists register is always set for master abort time-outs. the error reporting mechanism (hard fail or serr#) is determined by bit 13 of this register. 11 82454kx: reserved. 10 82454kx: reserved. 9 report host bus time-out errors enable. 1=enable. 0=disable. when enabled, the error reporting mechanism (hard fail or serr#) is determined by bit 13 of this register. note that the pb normally returns all 1s to cpu read transactions that receive a time-out. bit 9 in the exerrsts register is set, regardless of whether the error is reported. 8 host bus time-out enable. 1=the pb responds to unclaimed host bus transactions when the bus watchdog timer expires. the time-out value can be programmed to either 1.5 ms or 30 ms. 0=disable watchdog timer. 7 aerr# to nmi enable. 1=enable. 0=disable. when enabled (and bit 8=1 in the captured system configuration values register and serr# is enabled in the pcicmd register), the pb (compati- bility pb in an 82454gx dual pb system) asserts the serr# signal when detecting aerr# signal asserted. note that, depending on the system architecture, the serr# signal can result in the generation of an nmi. the nmi signal is not part of the pb and is typically provided by a pci-to-isa or pci-to-eisa bridge. 6 berr# to nmi enable. 1=enable. 0=disable. when enabled (and bit 9=1 in the csconfv register, offset b4Cb5h), the pb (compatibility pb in an 82454gx dual pb system) asserts the serr# signal (which can result in an nmi) when berr# is asserted. note that the nmi signal is not part of the pb. nmi is typically provided by a pci-to-isa or pci-to-eisa bridge. 5 reserved. 4 berr# to binit# enable. 1=enable. 0=disable. when enabled, the pb asserts binit# when berr# is asserted. 3 assert binit# on detection of host bus protocol violations enable. 1=enable. 0=disable. 2 assert berr# on bus errors enable. 1=enable. 0=disable. 1 reserved. planned use is aerr# to berr# enable. 1=enable. 0=disable. 0 assert aerr# on request phase signal parity errors enable. 1=enable. 0=disable. 82454gx: report uncorrectable host data bus ecc errors. 1=report by berr# signal (bit 2 must be set to 1). 0=disable 82454gx: single-bit ecc error correcting of host data bus enable. 1=enable. 0=disable. for the 82454gx in a dual pb system, this bit only has affect in the compatibility pb and has no affect in the auxiliary pb caution: programming this bit must be consistent with the value in the corresponding bit of the csconfv register captured from the host bus. otherwise, incorrect system operations will result. caution: programming this bit must be consistent with the value in the corresponding bit of the csconfv register captured from the host bus. otherwise, incorrect system operations will result.
preliminary 55 a 82454kx/gx (pb) 2.4.39 exerrsts?pb extended error reporting status address offset: c4Cc7h default: 0000 0000h attribute: read/write clear this register reports certain host bus error conditions. software sets each error condition to 0 by writing 1 to it. bits description 31:21 reserved. 20 received hard failure response. 1=host bus hard failure response or a second aerr# assertion was received for a pb initiated transaction. (exceptionthe pb does not log a hard fail response by another host bus agent to a pb posted write. the host bus agent error registers must be checked to determine the cause of the error.) 19 host bus address parity (ap#) error detected. this bit is set when an ap# parity error is reported by the 82454. 18 host bus request parity (rp#) error detected. this bit is set when an rp# parity error is reported by the 82454. 17 82454kx: reserved. 16 host bus protocol violation detected. this bit is set when a protocol violation, including rs parity errors, is reported by the 82454. both opbs check for protocol violations in dual-bridge 82454gx systems. 15:12 reserved. 11 82454kx: reserved. 10 reserved. 9 time-out on host bus detected. 1=the pb detected a time-out (no response phase within the time-out value programmed into the pbc resister (4ch) and in-order queue not empty) on the host bus. this bit is set, regardless of whether the event is reported. this bit is not used in the auxiliary bridge of a dual pb system. 8:4 reserved. 3 binit# on host bus detected. 1=binit# was detected on the host bus. 2 berr# on host bus detected. 1=berr# was detected on the host bus. the pb (compatibility pb in an 82454gx dual pb system) generates a serr# if enabled via bit 7 of the exerrcmd register, or the pb generates binit if berr# to binit# is enabled via bit 4 of the exerrcmd register. 1 reserved. 0 aerr# on host bus detected. 1=aerr# was detected on the host bus. the pb (compatibility pb in an 82454gx dual pb system) generates serr#, if enabled via bit 7 of the exerrcmd register. no recovery is possible as there is a chance of data corruption. 82454gx: host bus correctable error detected. 1=logs a single-bit ecc error detected on the data bus. no error is reported when a host bus correctable error is detected. 82454gx: host bus uncorrectable error detected. 1=logs a multiple-bit ecc error detected on the data bus. note that this bit is set independent of whether error reporting is enabled via bit 11 of the exerrcmd register. if berr# is enabled in the csconfv and exerrcmd registers, this error is reported by generating a berr#.
56 preliminary 82454kx/gx (pb) a 2.4.40 pbrtmr?pb retry timers address offset: c8h default: 0000 0003h attribute: read/write this register configures the host bus retry counter operation and the pci retry counter operation. bits description 31:16 host retry counter value. this field is programmed with the retry count value. the count is in host bus clocks. 0000h disables the counter. the pb re-enables inbound posting after an outbound read transaction is retried if the retried agent does not return before this count expires. 15:5 reserved. 4:2 pci retry count value. posting is re-enabled when this count expires. note that this count should match the count in the external pci arbiter, if the arbiter has a retry masking counter. bits[4:2] pci clocks bits[4:2] pci clocks 000 0 011 64 001 16 100 128 010 32 101C111 reserved 1 re-enable posting after an inbound transaction is retried enable. 1=enable posting when count expires. 0=disable (ignore pci retry counter). this bit may be set along with bit 0. 0 re-enable posting after an inbound transaction is retried. 1=re-enable posting as soon as pci bus parking is observed. 0=ignore state of pci bus parking.
preliminary 57 a 82454kx/gx (pb) 3.0 pb functional description this section describes the pb functions and hardware interfaces including the i/o and memory map, host bus, pci bus, and dual-bridge architectures. data integrity and error handling are covered. clock, reset, and pb configuration are also covered. 3.1 memory and i/o map the 82454kx/gx pb provides the interface between the host bus and the pci bus. memory transactions can be sent from the pci bus to the host bus and from the host bus to the pci bus. gaps and positive decode ranges can be programmed via the configuration registers. for the 82454kx, i/o transactions can be sent from the host bus to the pci bus. however, i/o transactions can not be sent from the pci bus to the host bus. if an access is enabled to be forwarded from the host bus to the pci bus, the corresponding access on the pci bus is ignored (not forwarded to the host bus). conversely, if an access is enabled to be forwarded from the pci bus to the host bus, the corresponding access on the host bus is ignored (not forwarded to the pci bus). the pb and mc perform a positive address decode of each host transaction and one default device handles the unclaimed transactions. in a standard pc system, unclaimed transactions are sent to the isa bus. thus, the pb (compatibility pb in an 82454gx dual pb system) is the default responder on the host bus. 3.1.1 memory address map the pentium pro processor memory address space is 64 gigabytes (36-bit addressing). the pb does not support transactions of address size larger than 36-bits whether directed to the pb or not. the pb registers that control the memory space access are: ? programmable attribute map (pam[6:0]) registers. these registers provide read only, write only, and read/write disable for fixed memory regions in the pc compatibility area. ? video buffer area enable (vba) register. this register enables the a0000Cbffff fixed region. ? top system memory (tsm) register. this register permits the pb (compatibility pb in an 82454gx dual pb system) to claim memory transactions above the top of main memory (top of memory to 64 gbytes) and forward these transactions to the pci bus. ? memory gap range registers (mgr and mgua registers). the memory gap range can start on any 1 mbyte boundary from 1 mbyte to 64 gbytes and can be 1, 2, 4, 8,16, or 32 mbytes. ? high memory gap range registers (hmgsa and hmgea registers). the high memory gap can start on any 1 mbyte boundary from 1 mbyte to 64 gbytes. ? high bios (hbios) register. the 64 kbyte region from f0000Cfffffh is treated as a single block and is normally read/write disabled in the mc(s) and read/write enabled in the pb. for the 82454gx, both memory and i/o transactions can be sent from the pci bus to the host bus and from the host bus to the pci bus. memory and i/o gaps and positive decode ranges can be programmed via the config- uration registers. after power-on reset, this region is read/write enabled in the compatibility pb and read/write disabled in the auxiliary pb. thus, the compatibility pb responds to fetches during system initialization.
58 preliminary 82454kx/gx (pb) a ? i/o apic range (apicr) register. this register provides an i/o apic configuration space. there is no i/o apic in the pb or the mc. note that, the address range between the apic configuration space and the high bios range (fed00000hCffdfffffh) is always mapped to local memory unless: 1) the range is above top of physical memory or 2) the high bios and apic ranges are disabled in the pb and the range falls within a memory gap range. ? pci frame buffer (pfb) register. the pci frame buffer range can start on any 1 mbyte boundary from 1C4 gbytes and can be 1, 2, 4, 8, 16,or 32 mbytes. ? smm range (smmr) register along with the smm enable (smme) register (only when smmem# is asserted). a pentium pro processor asserts smmem# in its request phase if it is operating in system management mode. the default smram area is an address range that is normally mapped through the pb to the pc compatible video graphics adapter. the pb ignores accesses to this overlaid address range when the smmr register is enabled and smmem# is asserted during host bus transac- tions. smm support. the pb supports system management mode by allowing the smram region in the mc to overlay addresses that are normally mapped to the pci bus. for cases where 64 kbytes is insufficient for a given application, smram can be relocated by the smmr register to a different start address set in 64 kbyte increments and a maximum range of 1 mbyte. the smmr register should also be used if the top of memory register is enabled and smram is placed above normal memory. the smmr register is programmed in this instance to ignore the smram range during smmem# accesses, but claim this range for normal accesses (smram range overrides top of memory). when the processor receives an smi#, it invokes an smi acknowledge transaction before entering the smi handler routine. the compatibility pb generates the response phase for an smi acknowledge transaction and also asserts the smiact# signal, if smmem# is asserted. once asserted smiact# remains asserted until an smi acknowledge transaction occurs with smmem# negated. see the host bus interface section for additional information on smm mode. memory mapped i/o. the pb allows memory addresses to be mapped to the host bus or to a pci bus below the pb. memory mapped i/o devices can be located anywhere in the pbs 64 gbyte address space. the frame buffer range allows the pb to decode memory mapped i/o space extending up to 4 gbytes. the memory space gap and high memory gap registers allow the pb to decode two address ranges extending up to 64 gbytes. host transactions to memory space. if a memory space address is in one of the above ranges, and that range is enabled, the pb claims the transaction and forwards it to the pci bus. accesses that are not in one of the enabled ranges and below the top of main memory are assumed to be accesses to main memory and are not claimed by the pb. the pb (compatibility pb in an 82454gx dual pb system) is responsible for any unclaimed transactions on the host bus. therefore, any memory space access that is above the top of main memory is claimed by this pb and forwarded to its pci bus, if enabled in the tsm register. otherwise, transac- tions that are not mapped to any host bus device will time-out. transactions that time-out on the host bus are handled by the pb (compatibility pb in an 82454gx dual pb system) to remove them from the in-order queue. these transactions are not forwarded to pci. pci transactions to memory space. all pci memory space accesses below the top of main memory (as programmed in the tsm register) are forwarded to the host bus, unless they are specifically directed to pci by one of the memory space access registers listed at the beginning of this section. in a dual pb system, the compatibility and auxiliary pb default to forwarding all pci memory space accesses above the top of memory to the host bus.
preliminary 59 a 82454kx/gx (pb) 3.1.2 i/o address map the pentium pro processor i/o address space is 64 kbytes. for the 82454kx, the pb maps all host bus i/o accesses to the pci bus, except for the confadd, confdata, and trc register locations. the pb registers that control the i/o space accesses are: ? confadd, confdata, and trc registers. these three pb registers are located in the processors i/o address space. see the register description section for details. ? pci decode mode (pdm) register. the pb optionally supports isa expansion aliasing. when isa expansion aliasing is enabled (via the pdm register), the ranges designated as i/o expansion are internally aliased to the 100C3ffh range before the i/o space range registers are checked. cpu transactions to i/o space. for the 82454kx, the pb claims all host bus i/o accesses and forwards the accesses to the pci bus, except for the confadd, confdata, and trc register locations. accesses to confadd (ocf8) must be dword aligned. i/o transactions targeting 0cf8h are treated as normal i/o trans- actions when they are not dword aligned. accesses to confdata (0cfch) are treated as normal i/o transac- tions when the configuration space enable bit of the confadd register is not set. isa expansion board aliasing. in pcs the i/o address range 100C3ffh is reserved for isa expansion boards. many isa expansion boards only decode address bits [9:0] which results in aliases of the decode range of these boards. the pb provides a method to route the alias of an address in the 100C3ffh range through the appropriate pb when i/o space has been split between dual pbs. see pci decode mode (pdm) register (offset 48h). pci transactions to i/o space. for the 82454kx, i/o space accesses are never forwarded to the host bus. for the 82454gx, the compatibility pb maps all host bus i/o accesses to the pci bus, except for i/o address ranges programmed into the iosr[2:1] registers (and the confadd, confdata, and trc register locations). in a dual pb system, the auxiliary pb ignores all host bus i/o accesses (except for the confadd and confdata register locations), unless forwarding is programmed into the iosr[2:1] registers. ? i/o space range registers (iosr[2:1]). two i/o space range registers (iosr1 and iosr2) permit the pb to forward transactions targeting that range to the pci bus. if an i/o space address is in either of the i/o ranges, and that range is enabled, the pb claims the transaction and forward it to the pci bus. for the 82454gx in a dual pb system, the compatibility pb is the default i/o response agent responsible for claiming all i/o transactions on the host system bus. therefore, any i/o address range that is mapped to an auxiliary pb must be disabled by an i/o range register in the compatibility pb. when using the i/o space range registers, the confadd, confdata, and trc registers (0cf8h, 0cf9h, and 0cfch) are treated differently than other i/o space addresses. i/o transactions targeting 0cf8h are treated as normal i/o transactions by the iosr[2:1] registers when they are not dword aligned transactions. accesses to 0cfch are treated as normal i/o transactions by the iosr[2:1] registers when the configuration space enable bit of the confadd register is not set. byte address ocf9h is recognized only by the compat- ibility pb, and is never affected by the iosr[2:1] registers. for the auxiliary pb in a dual pb system, all pci i/o space accesses are forwarded to the host bus unless they are specifically directed to pci by one of the i/o range registers. for the compatibility pb, i/o space accesses are never forwarded to the host bus, unless specifically directed to the host bus by one of the i/o range registers. the pb never forwards pci i/o accesses greater than 64 kbytes to the host bus.
60 preliminary 82454kx/gx (pb) a 3.2 host bus interface the pentium pro processor bus provides an efficient, reliable interconnect between multiple pentium pro processors and the pb and mc. the bus provides 36 bits of address, 64 bits of data, protection signals needed to support data integrity, and the control signals to maintain a coherent shared memory in the presence of multiple caches. the pentium pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans- actions and deferred replies. a single pentium pro processor may have up to four transactions outstanding at the same time, and can be configured to support a total of either one or eight transactions active on the pentium pro processor bus at any one time. the pb supports up to eight active transactions on the host bus (in-order queue depth of 8). during the host bus reset and configuration, all host bus devices are configured to support either one or eight transactions in their in-order queue. the number of transactions that can target a particular bus client is configured separately from the total number of transactions allowed on the bus. the pb accepts up to four transactions into the outbound request queue that target its associated pci bus. the pb provides four 32-byte buffers for outbound data (host-to-pci writes or pci reads from the host bus), and four 32-byte buffers for inbound data (pci-to-host writes or cpu reads from pci). as a host bus master, the pb does not support deferred responses. the exf1# extended function signal (defer enable) will never be asserted for a host transaction initiated by the pb. the host bus supports ecc over the data bus, and parity protection over the address, request, and response lines. the pb generates and checks ecc over the data lines (82454gx only), and generates and checks parity over the address and request/response signal lines (both 82454kx/gx). note, ecc generation and checking on the data lines and parity generation and checking on the request/response lines can be enabled or disabled during system configuration. note: 1. the pb is a non-caching agent and does not participate in the snoop phase. the write back (wb) memory types can not be mapped through the pb (snoop write-back data is ignored by the pb for implicit writebacks initiated by other agents). no wb memory types should be mapped to pci. for pci frame buffers, the write combining (wc) memory type is recommended. 2. the pb is a non-caching agent; however all pentium pro processor commands are defined for the pb. therefore read invalidate transactions are treated as reads by the pb. write invalidate cycles are treated as writes of length 0 by the pb. write-backs initiated by other agents are ignored by the pb. 3. when the processor receives an smi#, it invokes an smi acknowledge transaction before entering the smi handler routine. the compatibility pb generates the response phase for an smi acknowledge transaction and also asserts the smiact# signal, if smmem# is asserted. once asserted smiact# remains asserted until an smi acknowledge transaction occurs with smmem# negated. the other system management mode transaction that is supported on the processor interface is stop clock acknowledge. the stop clock acknowledge is an indication from the processor to the system that the processor is powering down the internal caches to save power. for stop clock acknowledge transactions, the compatibility pb is the responding agent and generates a stop clock grant special cycle on its pci bus. 4. if the smram space is set up as writeback memory, a wbinvd instruction must be executed in the smm handler immediately before execution of the rsm instruction that exits smm mode.
preliminary 61 a 82454kx/gx (pb) 3.3 pci bus interface the pb has a standard master/slave pci bus interface. all legal pci (pci specification 2.0) bus transactions are supported. pci cycle termination and error logging/reporting are discussed in the data integrity and error handling section. the pci arbitration unit is not implemented in the pb. pci locks. systems which support pci initiate locks (either inbound locks or peer-to-peer) must configure the arbiter for full bus locks rather than resource locks. the pb will not recognize resource locks made by peer-to- peer accesses. when a pci master asserts lock# while targeting the pb, the locked pci transactions are converted to locked host bus transactions. the host bus lock continues as long as the pci master asserts lock# for exclusive access to the pb. the host bus lock is assisted by the bridge continuing to assert bpri# as long as the pci bus is asserting resource lock to the bridge. additional locked cpu transactions are issued if the pci master continues to burst. in systems in which target abort reporting is disabled, the write portion of a lock will be committed even when the read portion is aborted. note: locks that cross cache line boundaries initiated on the pci bus will not generate a splck# signal on the host bus. this should be understood by all host bus agents. neither the pb nor the mc require splck# assertion. host bus locks. any transactions that target the bridge during a host bus lock are converted into a similar pci lock transaction. the lock on the pci bus is held until the host bus lock is released. locks over the frame buffer region can be disabled through a mode bit in the pci frame buffer range register. note: locks that split across pci host bus device boundaries (originate to one device and complete to another) are only supported for shadowed memory, and then only behind the compatibility pb. shadowed memory is memory mapped for read only or write only in the mc and the opposite way in the pb. an update may be required for older non-pci 2.0 compliant device drivers to comply with this. since the revision 2.0 of the pci specification does not allow locks to cross device boundaries, this will not be an issue with new device drivers. indivisible operations. cpu initiated read operations that cross a dword boundary (e.g., read 8 bytes, read 16 bytes, etc.) are indivisible operations on the host bus. however, since the pci protocol allows a target device to disconnect at any point in a transfer sequence, these operations must be locked indivisible on the pci bus. the pb optionally locks all cpu initiated reads that cross a dword boundary. this mode is enabled by setting the lock atomic reads in the pb configuration register. cpu initiated write operations (e.g., write 8 bytes, write 16 bytes, etc.) are indivisible operations on the host bus. however, these accesses can not be made indivisible on the pci bus because the pci specification states that the first transaction of a locked operation must be a read. therefore, software must not rely upon the atomicity of cpu initiated write transac- tions greater then 32 bits once they are translated to the pci bus. software generated special cycles. this optional feature is not supported by the 450kx/gx pciset.
62 preliminary 82454kx/gx (pb) a 3.4 data integrity and error handling several data integrity features are included in the pb. these include ecc on the host data bus (450GX only), parity on the host address, parity on the cpu request/response signals, and parity on the pci bus. error logging (setting a status bit) and reporting (generating an error signal) are controlled by the pcicmd register (04C05h), pcists register (06C07h), errcmd register (70h), errsts register (71h), exerrcmd register (c0Cc3h), and exerrsts register (c4Cc7h). 3.4.1 host bus errors the pb detects errors on the host bus by checking the ecc provided with data (450GX only) and the parity provided with control signals. in turn, the pb will generate ecc with data (450GX only) and parity with control signals so that bus errors can be detected by receiving clients. request parity (rp#) is the parity signal for ads# and req[4:0]# and is computed as even parity. ap[1:0]# are the parity signals for a[35:3]# and are computed as even parity (ap1# is for a[35:24]# and ap0# is for a[23:3]#. rsp# is the parity signal for rs[2:0]# and is computed as even parity. in addition, certain host bus protocol violations are detected by the pb. the pb (compatibility pb in a 82454gx dual pb system) is responsible for responding to any unclaimed trans- actions on the host bus. the pb uses a watchdog timer to monitor host response phases. the timer is started at the end of a response phase if the in-order queue is not empty. if the timer expires before the next host response phase, a host bus time-out has occurred. the time-out window for such an event is programmable to 1.5 or 30 milliseconds via the pbc register (4ch). this allows for several host to pci transactions, which may be blocking the progress of the in-order queue, to undergo multiple retries. when a host bus time-out occurs, the pb (compatibility pb in an 450GX dual pb system) claims the transaction by returning all 1s to a read transaction or pretending to accept data for a write transaction. this event is logged in the exerrsts register and can generate a hard fail or serr#, if enabled in the exerrcmd register. aerr#. if aerr# observation is enabled, then aerr# to nmi should be enabled in the exerrcmd register (c0-c3h). this allows software to accept an nmi to log or recover from the event. binit#. a binit# on the host bus creates a pcirst# and resets the 450kx/gx pciset host bus state machines. this allows for logging or recovery from catastrophic bus errors. 3.4.2 pci bus errors the pb always detects address parity errors when it is not the pci master, even if it is not the selected target. the pb detects data parity errors if it is either the master or the target of a transaction, and optionally reports them to the system. address parity errors are reported using the serr# signal. data parity errors are reported using the perr# signal. on the 450GX, ecc error checking is used for the data bus. the ecc check bits are provided by the dep[7:0]# signals.
preliminary 63 a 82454kx/gx (pb) 3.4.2.1 pb master operation on pci master abort. when the pb performs a master abort, if the command was not a special cycle, the event is logged by setting the received master abort bit (bit 13) in the pcists register. an interrupt can be generated on this event. special cycle commands, which are broadcast to all pci targets, are always terminated with master abort. therefore, master aborts during special cycle commands are not considered errors, and are never logged or reported. target disconnect and target retry. target disconnects and target retries are not errors, and are not logged or reported. ta rg et a bo r t. the pb logs a target abort by setting the received target abort bit (bit 12) in the pcists register. if the serr# enable bit (bit 8) of the pcicmd register is set, and the serr# on receiving target abort bit (bit 7) of the errcmd register is set, this event is reported by asserting serr#. when the pb asserts serr#, the signalled system error bit (bit 14) in the pcists register is set. optionally, the pb reports a hard failure response to the host bus transaction (pb exerrst register). note that this is not possible for posted writes because the response phase has already occurred. data parity errors. as a pci bus master, the pb checks the data parity provided during read data cycles and monitors perr# during write data cycles. the errors are logged by setting the appropriate status bits. if a parity error is detected, the detected parity error bit (bit 15) in the pcists register is set. to distinguish between read data parity errors and write data parity errors, the appropriate bit (bit 6 for writes, bit 5 for reads) is set in the errsts register. errors are reported via the serr# and perr# signals. the conditions causing the assertion of serr# due to data parity errors are summarized in figure 5. the conditions causing the assertion of perr# and the detected parity error status bit are summarized in figure 3 and figure 4. note that for read data parity errors, the pb returns the corrupted data (with good parity/ecc) as the cpu read response data. for write data parity errors, the corrupted data has already been delivered to the target; it is not retried by the pb. 3.4.2.2 pb target operation on pci target disconnect . pb generated target disconnect is not considered an error and is not logged or reported. target retry . target retry is not an error and is not logged or reported. the pci master is responsible for deter- mining the maximum number of retries. ta rg et a bo r t. when the pb issues a target abort it sets the signaled target abort bit (bit 11) in the pcists register. no further reporting or logging is done by the pb. the pci initiator logs the target abort and may report the error. data parity errors . as a target on the pci bus, the pb checks the data parity provided during write data cycles. if a parity error is detected during write data cycle, perr# is asserted and bit 15 of the pcists register is set. no further reporting or logging is done by the pb. . figure 3. logic diagram of the assertion of perr# data parity error parity error responses enabled perr# 04h[6] 70h[3] perr# on data parity error enabled
64 preliminary 82454kx/gx (pb) a . figure 4. logic diagram of the setting of the detected parity error bit0 figure 5. logic diagram of the assertion of serr# set for pci status bit 15 inbound data parity error perr# asserted on write data parity error (detected parity error) read data parity error parity error responses enabled serr# driver enabled serr# on received parity error enabled write data parity error parity error responses enabled serr# on transmitted parity error enabled serr# master abort received target abort received enable watchdog time-out set/observed aerr# set/observed berr# report errors using serr# report errors using serr# report master aborts serr# on received target abort report errors using serr# report watchdog time-out aerr# to nmi berr# to nmi 04h[6] 04h[6] c0h[9] 70h[5] 70h[6] coh[12] 70h[7] !coh[13] !coh[13] c0h[13] coh[7] coh[6] 04h[8] address parity error serr# on address parity error enabled parity error responses enabled 04h[6] 70h[4] c0h[8]
preliminary 65 a 82454kx/gx (pb) 3.5 dual pb architectures (82454gx only) in a dual bridge system, one pb is configured as the default bridge (compatibility pb) after power-on reset. the compatibility pb provides a path to the isa bus devices needed in a pc-compatible system such as the boot rom. the compatibility pb is the highest priority bridge in a dual bridge system to ensure a fast enough response time for isa bus masters. see the clocks, reset, and configuration section for details on config- uring a pb as the compatibility pb. multiple i/o apics in a dual pb system, the auxiliary pci bus interrupt requests are routed to the auxiliary bus i/o apic. when booting the system with one processor, the irq control logic is enabled, feeding the interrupt request to the standard interrupt controller in the esc. when the system is in multiprocessor mode, the routing logic is disabled after ensuring pb buffer coherency, and interrupt requests are forwarded to the processors via the apic bus. the intel 82379ab (sio.a) may be utilized as a stand-alone i/o apic device. however, the additional logic for interrupt/memory consistency and the interrupt steering logic is not provided in the sio.a and must be implemented externally. dual bridge arbitration for the host address bus the pb requests the host address bus with bpri#. however, only one bridge is allowed to drive bpri# at a time. with two pbs, an internal arbiter is used to establish bus ownership. this arbitration is transparent to the cpu and other symmetric bus agents. in a two pb system, the compatibility pb acts as the arbitration unit between it and the other pb, as shown in figure 6. when a pb is programmed to be the arbitration unit, its iognt# is the input for the ioreq# from the other bridge and ioreq# is the output to iognt# of the other bridge. figure 7 shows the minimum arbitration timing in a two bridge system. iognt# may assert later than shown and ioreq# may negate later than the two clocks after iognt# negates. the arbiter bridge can assert bpri# as long as it has not asserted its ioreq# (grant to the other bridge) and bpri# is not currently driven. in turn, the other bridge, after receiving its iognt#, samples bpri# released before assuming ownership of bpri#. this allows the bpri# arbitration to be performed in parallel with another bridge transfer. this timing is shown in figure 8. bridge-to-bridge misaligned (split) locks are not recommended and could cause deadlock in systems.
66 preliminary 82454kx/gx (pb) a figure 6. dual bridge system configuration . figure 7. bpri# arbitration timing host bus a_flshbf# (pullup to 3.3v) pci arbiter custom logic i/o apic device and irq memory logic pci bus 2 pci bus 2 irqs irq control logic compatibility pb auxiliary pb pceb esc c_flshbf# c_memreq# pci bus 1 c_memack# intr apic bus a_memreq# (pullup to ground) 12345678 9 10 bclk ioreq# iognt# bpri# ads# other bridge asserts ioreq# compatibility bridge asserts its ioreq# to indicate grant. other bridge asserts bpri# ioreq# and iognt# refer to the bridge making a request to the compatibility pbs arbiter. (earliest) other bridge de-asserts bpri# (earliest) other bridge asserts ads#
preliminary 67 a 82454kx/gx (pb) figure 8. bpri# arbitration overlapped with bridge transfer dual pb configuration (82454gx only) figure 9. iognt# & ioreq# pull-ups/pull-downs (dual bridge system) 12345678 9 10 ioreq# iognt# bpri# ads# bclk compatibility bridge asserts bpri# other bridge sees bpri# released other bridge asserts bpri# compatibility bridge asserts ads# other bridge asserts ads# other bridge asserts ioreq# compatibility bridge asserts ioreq# indicate grant to other bridge ioreq# and iognt# refer to the bridge making a request to the compatibility pbs arbiter. bridge-to-bridge communication pb-to-pb communication is supported by the pb, but is not recommended for optimal performance. pb-to-pb transactions involving a standard bus bridge (sio, pceb/esc) require special precautions to avoid deadlock and latency problems. the pb does not support pb-to-pb transactions from agents that cannot be backed off such as those originating on an isa or eisa bus and targeting a device on a different pbs pci bus. any device that asserts flshbuf# must be targeting a device on the local pci bus or the host bus. during a power-on reset (pwrgd asserted), ioreq# and iognt# provide a unique identification number for each pb (pbid). the pbid is part of the pbs pci bridge device number and is available to programmers via the bdnum register (offset 49h). the dual pb system must have a pull-up and a pull-down as shown in figure 9. the encoding for these signals is shown in table 10 ioreq# iognt# ioreq# iognt# vcc auxiliary compatibility bridge bridge
68 preliminary 82454kx/gx (pb) a . 3.6 peripheral operation and performance the 82454 pb is designed for optimum processor performance to get the most out of a pentium pro processors capabilities. in systems with multiple pci devices, one must take into account the architecture of the 82454 pb in order to maximize overall system performance. 3.6.1 matching peripherals to the 450kx/gx the 82454 pb is optimized for use with high performance pci peripherals. support for multiple cpus and multiple 82454 pbs comes at the cost of greater latency to system memory, which must be offset by more efficient use of the pci bus to achieve high bandwidth i/o throughput. for best system performance, only devices meeting the following criteria should be used in conjunction with the 82454 pb: 1. high throughput peripherals should be pci bus masters that control their own dma. peripherals which act as bus masters transfer data to and from memory with minimal intervention from the cpu. the available bandwidth for such devices is considerably greater than that available to programmed-i/o devices, which require the cpu to transfer data on their behalf. bus mastering devices also allow the cpu to pursue other work in parallel with i/o transfers from pci, resulting in higher overall system efficiency. finally, outbound traffic from the cpu interferes with inbound bus mastering transactions, as they both compete for ownership of the 82454 pb. the latter effect implies that one non-mastering device can adversely impact the performance of several other mastering devices. 2. peripherals should support the advanced pci command subset. the advanced pci commands are memory read line (command encoding e ), memory read multiple (command encoding c ), and memory write and invalidate (command encoding f ). devices utilizing these commands differentiate between long data transfers and short overhead transfers, and use appropriate pci commands for each. further, such devices tend to implement sufficient on-board data fifo space to support full-speed pci burst transfers greater than a cache line in length. 3. latency-sensitive peripherals should provide adequate data buffering. peripherals such as network interface cards have a latency requirement once transmission has begun. if they cannot buffer sufficient data on board prior to initiating a transfer, they are subject to transmission under-runs when competing i/o subsystem activity causes the bandwidth across the wire to exceed the bandwidth into system memory. a similar scenario occurs in the opposite direction if the bandwidth into system memory falls below the band- width across the wire. for example, a pci card supporting fast ethernet at 100 mbit/sec, should provide at least 128 bytes of data buffering for transfers in each direction. table 10. bridge device number encoding iognt# ioreq# pbid (bdnum register) description high low 01 compatibility pb low high 10 auxiliary pb in a two pb system
preliminary 69 a 82454kx/gx (pb) 3.6.2 distributing peripherals within the i/o subsystem while this is not necessary for system operation, systems implementing dual 82454 pbs have additional latitude to isolate high speed i/o devices from competing system traffic initiated by the cpu. all graphics and the vast majority of i/o space communication (such as keyboard controller, system timer, and interrupt support) will be directed to the primary pci bus behind the compatibility 82454 pb. (this is the bus with a subsequent connection via another bridge to an isa or eisa bus.) this processor traffic will compete with bus mastering peripheral devices attempting to move data to and from system memory. it is desirable then to place latency sensitive devices behind the auxiliary 82454 pb, to isolate them from competing cpu traffic. in a full system configuration, in which all pci slots are occupied, it is preferable to segregate peripherals intel- ligently. limit the primary pci bus to graphics accelerators and scsi raid controllers, leaving auxiliary 82454 pb pci slots free for latency-sensitive devices such as network adapters. in systems connecting a large number of network adapters, divide them evenly between the two busses to minimize the amount of latency- sensitive competition at any one point in the system. 3.6.3 pci-to-pci bridges since pci-to-pci bridge (p2p) components are a popular mechanism for increasing the connectivity of a pci subsystem, the issues associated with using them should be understood. note that these components are not only used on motherboards, but are sometimes used on pci adapters as well. the hierarchical bus added into the system in this manner must compete with all other devices on the primary bus for bandwidth. further, the devices sharing the additional pci bus connected via the p2p must compete with each other for serial service across the p2p bridge. this means that peripherals placed behind a p2p device will perceive higher latency to memory and will be limited to shorter burst transfers; a condition which may cause errors in latency-sensitive peripherals. finally, if a p2p device in use is not fully compliant with the pci 2.1 specification, the system is exposed to unresolvable conflicts between multiple bus masters issuing transactions attempting to cross between the hierarchical pci busses. to eliminate the possibility of a resulting livelock failure, the system must operate with cpu-pci write posting disabled. this will degrade the performance of outbound traffic such as graphics, but will not adversely affect the performance of bus mastering i/o devices. 3.6.4 bios performance tuning specific system configurations each have an optimum set of performance feature settings, but the following recommendations establishes a good baseline to begin system tuning. the system designer should tune the read prefetch enable bits in the 82454 to avoid wasted host bus bandwidth due to short reads that do not make use of prefetched data. most pci peripherals which implement the advanced pci command set also use these commands as recommended in the pci specification. specifi- cally, pci masters should use the pci memory read command for transfers less than a cache line in length, the pci memory read line command for transfers of one or two cache lines, and the pci memory read multiple command for transfers of two or more cache lines. given no specific data on the peripherals to be used in the system, the bios should default to a configuration which assumes that pci peripherals will behave as described above. that is, enable the line read alias bits for all pci read command types, but only enable the read prefetch bit for the pci memory read multiple command. this configuration may be modified, perhaps in a setup utility, if that provides better performance for a given set of devices.
70 preliminary 82454kx/gx (pb) a the relatively high latency to memory in 450kx/gx-based systems will require larger pci master latency timer values than the typical 32 clock default. in order to allow each master the opportunity to burst multiple cache lines per transfer, the master latency timer (mlt) of each pci master in the system should be set to a value between 48h and 60h. (note that an mlt setting that is arbitrarily larger than 60h will allow a master capable of extremely long pci bursts to adversely impact the performance of other masters with more limited burst capability.) 3.7 clock, reset, and configuration 3.7.1 system clocking the pb operates in two clock domains. the pb interface to the host bus operates at the host bus clock frequency. the host bus clock is generated externally and distributed to host bus components by a low skew clock driver. the clock driver provides multiple copies of the bus clock. the pb receives its copy of the host bus clock through the bclk input pin. the pb interface to the pci bus operates at the pci bus clock frequency. the pci bus clock is generated internally by the pb and is ? the frequency of the host bus clock frequency. this output is designed to drive a single load and must be distributed by an external low skew clock driver. the external clock driver provides multiple copies of the bus clock. the pb receives a matching copy of the skewed pci bus clock through its pclkin pin. 3.7.1.1 host bus clock host bus clock distribution is shown in figure 10. the loading on the host bus clock lines must be balanced in order to minimize clock skew among the components on the host bus. this may require adjustment of clock line lengths. note that the bclk input to the pb must be running for 10 clocks before the assertion of pwrgd. figure 10. host bus clock distribution y1 y2 y3 yn external low skew clock generator/driver bclk host bus clk y4 y5 pb to mc and other system components
preliminary 71 a 82454kx/gx (pb) 3.7.1.2 pci clock pci clock distribution is illustrated in figure 11. an external 10k w pull-up resistor is required to place the pb in derived clock mode (only mode supported). the pb provides a pci bus clock that is generated by dividing the processor clock frequency by two. the phase of the pclk signal is matched to the host clock. externally, this pci clock drives a low skew clock driver which in turn supplies multiple copies of the pci clock to the pci bus. one of the outputs of the external clock driver is fed back to the pb. this copy is expected to meet the skew requirements of the pci specification. a pll in the pb forces the external pci clock to phase lock to the internal pci clock tree. figure 11. pci clock distribution 3.7.2 system reset power-on reset when the system is initially powered, the power supply must wait until all voltages are stable for at least one millisecond, and then assert the pwrgd signal. note that bclk must be running to the pb for 10 clocks before the assertion of pwrgd. the pb captures their bridge device number identification when pwrgd is asserted (see pb configuration section). while reset# is asserted, the pb resets and initializes its internal registers to the default state. the pb also initializes the pci busses by asserting pcirst# for a minimum of one millisecond. while reset# is asserted, the pb (compatibility pb in an 82454gx dual pb system) drives the appropriate host data bus signals with the values specified in the configuration values driven on reset register. in addition to asserting reset#, the pb (compatibility pb in an 82454gx dual pb system) also asserts creset# and continues to assert creset# two clocks longer than reset#. creset# may be used to select a mux that drives the host bus clock to core clock ratio onto pins lint[1:0], ignne#, and a20m# of the cpu during reset#. a y1 y2 y3 yn external low skew clock driver pclk pclkin pb vcc initially all pbs assert reset# until the id is captured and the compatibility pb is established. the compati- bility pb continues to assert reset# for a minimum of one millisecond and reset# becomes an input for the auxiliary pb; however, it does not affect their captured id.
72 preliminary 82454kx/gx (pb) a programmed hard reset the pb (compatibility pb in an 82454gx dual pb system) can be programmed to deliver a hard reset (assert reset#) to the host bus through the trc register. note that the internal register values are reset. programmed soft reset (init#) the pb (compatibility pb in an 82454gx dual pb system) can be programmed to deliver a soft reset (init#) to the processors through the trc register. note that the internal register values are preserved. programmed pci bus reset the pb (both pbs in an 82454gx dual pb system) can be programmed to reset their pci buses (assert pcirst#) without resetting the host bus (via the pci reset register). note that internal register values are preserved. programmed cpu bist the pb (compatibility pb in an 82454gx dual pb system) can be programmed to put the processor into bist mode via the trc register. cpu bist is triggered by performing a hard reset and having the init# signal asserted on the edge that reset# is released. note all 450kx/gx pciset devices are reset during the hard reset portion of this operation. 3.7.3 system initialization all host bus devices must sample the following configuration options at reset: ? address/request/response parity checking: enabled or disabled ? aerr detection enable ? berr detection enable ? binit detection enable ? frc mode: enabled or disabled ? power-on reset vector: 1m or 4g ? in-order queue depth: 1 or 8 ? apic cluster id: 0, 1, 2, or 3 ? symmetric agent arbitration id: 0, 1, 2, 3 the mc provides the symmetric arbitration id parameter. the pb provides some of the other parameters. see configuration values driven on reset register. 3.7.4 dual pb configuration (82454gx only) during a power-on reset (pwrgd asserted), ioreq# and iognt# provide a unique identification number for each pb (pbid). see dual pb architectures section for details.
preliminary 73 a 82454kx/gx (pb) 3.7.5 using the 82379ab sio.a pci-to-isa bridge with the 450kx/gx there is an anomaly with systems that use the 82379ab (sio.a) during targeted pci resets. in addition, 450GX/kx systems can boot improperly at power-up and react improperly to the assertion of the pentium pro bus signal binit# signal (due to the assertion of pcirst# via binit#). the sio.a drives smi#, alt_a20, int, nmi, ignne#, alt_rst#, and stpclk# low while pcirst# is asserted low, and does not drive them high until after pci reset is released. an anomaly can exist with these seven signals remaining low during and immediately after pcirst# is negated. the three instances in which this can cause an anomaly are: during a targeted pci reset, and in a 450GX/kx-pentium pro processor system, both during power-up and when binit# is asserted on the pentium pro processor bus. power-up during power up of an 450GX/kx-pentium pro system, the opb negates pcirst# and reset# (to the pentium pro) simultaneously. the delay in negating these seven signals after pcirst# is driven inactive can cause these signals to be sampled active low by the pentium pro when reset# (to the pentium pro) is released. ? smi#: when smi# is sampled low at power-up, the pentium pro attempts to jump to the smi handler instead of to the boot vector. an external solution is necessary to avoid this erroneous power-up condition. essentially, smi# must be blocked from being sampled low by the cpu when reset# is driven inactive. if smi# is not being used, the smi# input to the cpu can be pulled high. for systems using smi#, the solution shown below on the smi# signal ensures that smi# is high when reset# transitions inactive. this solution is not needed in systems using pentium pro b0 stepping (or later). these steppings of the pentium pro will not sample these seven inputs for at least 300ns after reset# is negated. ? alt_rst#: the cpu will reset again (generates init# to the pentium pro). this signal must be blocked. this solution is not needed in systems using pentium pro b0 stepping (or later). these steppings of the pentium pro will not sample these seven inputs for at least 300ns after reset# is negated. ? int: not an issue since this signal remains low following pcirst#. ? nmi: not an issue since this signal remains low following pcirst#. ? ignne#: has no affect on the processor when sampled low during power-up. ? alt_a20: has no affect on the processor when sampled low during power-up. ? stpclk#: has no affect on the processor when sampled low during power-up. binit# assertion when binit# is asserted by an agent on the pentium pro processor bus, the 82454kx/gx asserts pcirst# to reset the pci bus. the sio.a drives smi#, alt_a20, int, nmi, ignne#, alt_rst#, and stpclk# low while pcirst# is asserted low, and does not drive these signals high until after pci reset is released. several of these signals must be blocked with external logic if the system architecture cannot handle them going low as a result of binit#. architectural considerations consist primarily of how the systems pentium pro processors have been configured to handle the assertion of binit# and how any external error handling logic might influence the need for blocking logic. all steppings of the pentium pro processor need these solutions (where appropriate) if binit# is to be handled. ? alt_rst#: the low assertion of this signal causes the pentium pro processor to be reset each time binit# is asserted on the pentium pro processor bus (this signal is combined with init# from the pb to generate the init# signal to the pentium pro processor). this signal must be blocked with external logic if the system architecture cannot handle this.
74 preliminary 82454kx/gx (pb) a ? int: not a problem since this signal remains low following pcirst#. note that any pending interrupts on this pin will be lost when the sio receives the pci reset. ? nmi: not a problem since this signal remains low following pcirst#. note that any pending interrupts on this pin will be lost when the sio receives the pci reset. ? ignne#: unless software or the system architecture can ensure that no floating point errors are generated during the pci reset, this signal must be blocked. ? alt_a20: designers must be aware that this signal will be driven (and remain) low during and following pcirst#. additionally, rstdrv is asserted during pcirst#. this sill cause the rstar# output of the keyboard controller to also be set low. these factors must be considered in any design implementing binit# functions. ? stpclk#: if the stpclk# function is enabled in the design, then this signal must incorporate blocking logic. ? smi#: if smi# is enabled in the design, then this signal must incorporate blocking logic. targeted pci resets systems that support targeted pci resets (resetting the pci bus via software control without resetting the microprocessor) may have a problem with some of the seven signals being asserted low during the targeted pci reset. since the microprocessor can not know when a pcirst is occurring, this fix must be incorporated in order to reset the pci bus via the register. this affects all designs using the sio.a. ? alt_rst#: the low assertion of this signal will cause the microprocessor to be reset each time the pci bus is reset (this signal is normally combined with a cpu soft reset pin from another component to generate the init# signal to the microprocessor). this signal must be blocked with external logic. ? int: not an issue since this signal remains low following pcirst#. note that any pending interrupts on this pin will be lost when the sio receives the pci reset. ? nmi: not an issue since this signal remains low following pcirst#. note that any pending interrupts on this pin will be lost when the sio receives the pci reset. ? ignne#: unless software or the system architecture can ensure that no floating point errors are generated during the pci bus reset, this signal must be blocked. ? alt_a20: designers must be aware that this signal will be driven (and remain) low during and following pcirst#. additionally, rstdrv is asserted during pcirst#. this sill cause the rstar# output of the keyboard controller to also be set low. these factors must be considered in any design implementing targeted pci resets. ? stpclk#: if the stpclk# function is enabled in the design and it is not desirable to have the cpu shutdown throughout the pci reset, then this signal must incorporate blocking logic. ? smi#: if smi# is enabled in the design, then this signal must incorporate blocking logic. the reset mask blocking circuit shown in figure 12 will block signal a from being seen by the cpu during the pci reset. the second flip flop is necessary to avoid a glitch on the z output to the cpu which can happen if signal a is asserted simultaneously with pcirst#. the blocking circuitry for all of the signals should be incorporated into a pld. this will ease loading on pciclk and pcirst#.
preliminary 75 a 82454kx/gx (pb) figure 12. blocking logic for 82420kx/gx designs using the 82379ab sio.a notes: 1. 5v to 3.3v translation is not shown. the system designer must ensure correct logic levels are provided. all pb outputs are 3.3 volt. alt_a20 1 smi# 1 q dq r q dq r pciclk a z pcirst reset mask 1 0 1 0 1 0 1 0 s reset mask az pciclk alt_rst# sio.a - 5 v 052053_4.ds4 reset mask az reset mask az reset mask az pb - 3.3v reset# flush# pwrgd init# creset# 8042 - 5v keyboard rstar# a20gate picclk (pentium pro processor) reset# (pentium pro processor) flush# (pentium pro processor) pwrgd 3 (lint0) 2 (lint1) 1 (ignne#) 0 (a20m#) smi# 1 stpclk# 1 picd[1:0] 1 ferr#/irq13 1 int 1 nmi 1 ignne# 1 stpclk# (pentium pro processor) 1 picd[1:0] (pentium pro processor) 1 ferr# (pentium pro processor) 1 init# (pentium pro processor) 1 lint0 (pentium pro processor) 1 lint1 (pentium pro processor) 1 ignne# (pentium pro processor) 1 a20m# (pentium pro processor) 1
76 preliminary 82454kx/gx (pb) a 3.8 host to pci bus command translation if a valid pentium pro processor bus command is directed at the bridge, the pb generates a pci bus request. when the pb is granted the pci bus, it issues a pci command after the commit point of the pentium pro processor bus transaction. pentium pro processor bus commands that are directed at the pb and conse- quently to the pci bus must be converted into appropriate pci bus commands. the pb is a non-caching agent on the host bus; however, it must respond appropriately to pentium pro processor commands that are cache oriented. table 11. host to pci bus command translation host bus command (asz = 36, dsz=64) other encoded information pci bus command deferred reply dont care none inta len: <= 8 bytes interrupt acknowledge with be[0] asserted. special cycles be: shutdown none be: stop clock acknowledge pci special cycle - stop clock grant be: all others none i/o read len: <= 8 bytes up to 4 bes asserted i/o read (one or two transactions) branch trace message none i/o write len: <= 8 bytes up to 4 bes asserted i/o write (one or two transactions) read invalidate dont care memory read line (8 dword burst starting with the low address) code read len: <= 8 bytes without all byte enables asserted memory read (one or two transactions) len: <= 8 bytes with all byte enables asserted memory read (2 dword burst starting with the low address) len: 16 bytes memory read (4 dword burst starting with the low address) len: 32 bytes memory read line (8 dword burst starting with the low address) memory read len: <= 8 bytes without all byte enables asserted memory read (one or two transactions) len: <= 8 bytes with all byte enables asserted memory read (2 dword burst starting with the low address) len: 16 bytes memory read (4 dword burst starting with the low address) len: 32 bytes memory read line (8 dword burst starting with the low address)
preliminary 77 a 82454kx/gx (pb) 3.9 pci to host bus command translation when a pci bus command is directed at the bridge, the pb generates a bpri# request or arbitrates for bpri# ownership if there are two bridges. the actual point in time when the bpri# is issued depends on a number of factors including whether the bridge accepted the pci request or forced a retry to the pci master, and when a complete cache line is filled during a write command. pci bus commands that are directed at the pb and consequently to the host bus are converted into the following appropriate host bus commands. central agent reserved transac- tions with no data. none reserved encodings these encodings are ignored. a bus time-out will complete the cycle memory write len: <= 8 bytes without all byte enables asserted memory write (one or two transactions) len: <= 8 bytes with all byte enables asserted memory write (2 dword burst starting with the low address) len: 16 bytes memory write (4 dword burst starting with the low address) len: 32 bytes memory write and invalidate or memory write (8 dword burst starting with the low address) table 12. pci to host bus command translation pci bus command host bus command memory read memory read len: 8 or len: 32 (when cpu line read for pci memory read commands [bit 8] is enabled in the pci read/write control register: 54-55h) memory read line memory read len: 8 or len: 32 (when cpu line reads for pci memory read line commands [bit 3] is enabled in the pci read/write control register: 54-55h) memory read multiple memory read len: 8 or len: 32 (when cpu line read multiple for pci memory read multiple commands [bit 5] is enabled in the pci read/write control register: 54-55h) table 11. host to pci bus command translation (continued) host bus command (asz = 36, dsz=64) other encoded information pci bus command
78 preliminary 82454kx/gx (pb) a notes: this includes special cycles. there is no mechanism to pass special cycles originating on the pci bus to the host bus. accesses to the confadd and confdata registers can be passed to the host bus if the pb is not programmed to accept cf8 and cfc transactions from the host bus. for the 82454gx in a dual pb system, this allows the auxiliary bridge to pass configuration commands to the host bus from its pci bus. in general, the length of pci master bursts is indeterminate unless the master can be programmed for specific burst lengths. the pci bridge takes advantage of the pci bursting capability by always trying to assemble the most efficient host bus size transfers. the bridge selectively asserts stop# (retry) to the pci master as posting buffers become unavailable. during pci master reads the bridge will attempt to make the most efficient use of the host bus by generating line reads or partial reads based upon the type of pci read occurring and the options programmed into the bridge configuration registers. memory write memory write len: 8 memory write and invalidate line write len: 32 (if pci-to-cpu write posting is enabled in bit 0 of the pci read/write control register. i/o read i/o read len: 8 i/o write i/o write len: 8 dual address translated up to a 36-bit host bus address. other command encodings all other command encodings 1 are ignored by the pb. table 12. pci to host bus command translation (continued) pci bus command host bus command
preliminary 79 a 82454kx/gx (pb) 4.0 pb pinout and package information 4.1 pin assignment there are two packages for the 82454kx/gx304 pin qfp and 352 pin bga. pins unique to the 450GX are shown in a list at the center of the figure. in the tables, the first name is the 450GX name. note that testlo pins must be pulled-low with a 150 w resistor and testhi pins must be pulled to 3.3v with a 10k w resistor. gtlhi pins should be pulled up with 10k w to v tt . figure 13. 82454 pin assignment (304-pin qfp) gnd d13# vcc3 gnd d11# d17# gnd a23# d16# a20# a21# a19# gnd d20# d18# d19# d22# d23# gnd d21# a28# a16# a15# a18# a3# vcc3 a11# a12# a25# gnd d10# d15# gnd d14# d9# a14# a13# a17# gnd gnd vcc3 d8# d7# d5# a10# a7# vcc3 gnd d0# d2# d1# d4# gnd a8# a5# a9# gnd d3# d6# memack# memreq# tck trst# recven tms gtlvref tdi pwrgd tdo gnd a4# a6# flshbuf# d12# gnd gnd 304pindt.drw 281 280 279 277 273 272 271 268 265 267 266 263 262 261 260 259 258 264 269 270 274 275 276 283 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 282 278 229 230 231 293 292 291 288 285 287 286 284 289 290 294 295 298 297 296 299 300 303 302 301 304 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 206 205 204 202 198 197 196 193 190 192 191 188 187 186 185 184 183 189 194 195 199 200 201 208 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 207 203 153 154 155 156 218 217 216 213 210 212 211 209 214 215 219 220 223 222 221 224 225 228 227 226 d55# gnd gnd d63# gnd gnd drdy# gtlhi gnd gtlhi gtlhi gtlhi gtlhi gnd gnd reset# gnd bclk gnd gtlhi gnd vcc3 gtlhi gtlhi flush# init# hit# gnd lock# hitm# dbsy# defer# gnd req3# gnd req1# gnd req4# bnr# gnd bpri# rsp# ap0# vcc3 vcc3 req2# gnd gnd berr# d62# d58# gnd trdy# ap1# req0# d61# binit# gnd vccpci gnd aerr# rs2# gnd ads# rp# smiact# vcc3 gnd rs1# rs0# gnd gnd pclk pclkin pgnt# preq# gnd a35# vcc3 vcc3 a26# a27# a24# a22# a34# gnd d25# d24# d26# d27# gnd a33# a30# a29# gnd d29# d30# d28# d31# d32# gnd reserved a32# a31# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 d48# gnd d38# d56# gnd d60# gnd d50# d53# d54# gnd d57# d59# gnd d46# gnd d49# d52# gnd d36# gnd d43# d40# gnd d37# vcc3 vcc3 d33# d34# gnd d35# d39# reserved reserved creset# gnd gnd d51# d41# gnd d42# d47# gnd d45# d44# gnd vcc3 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 vcc3 ad7 gnd vcc3 testlo testlo vccpci ad0 testhi testlo ad1 ad2 gnd vcc3 ad3 vccpci ad5 ad6 ad8 c/be0# ad9 vccpci ad10 ad11 vcc3 ad4 pcirst# ad23 perr# ad15 ad31 vccpci ad30 ad29 gnd ad26 ad25 ad24 c/be3# gnd vcc3 ad22 frame# vcc3 gnd ptrdy# devsel# plock# gnd serr# par vccpci ad14 c/be1# irdy# ad12 ad13 gnd ad21 vccpci ad20 ad19 ad18 gnd ad17 ad16 c/be2# vccpci stop# vcc3 vcc3 ad28 ad27 vcc3 82454gx 162 163 165 166 168 169 170 173 296 297 dep7# dep2# dep4# dep1# dep6# dep5# dep0# dep3# ioreq# iognt# 82454 pb qfp reserved reserved reserved
82454kx/gx (pb) a 80 preliminary table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) signal pin # type a3# 15 i/o a4# 16 i/o a5# 27 i/o a6# 17 i/o a7# 28 i/o a8# 26 i/o a9# 29 i/o a10# 18 i/o a11# 43 i/o a12# 45 i/o a13# 42 i/o a14# 44 i/o a15# 54 i/o a16# 55 i/o a17# 41 i/o a18# 53 i/o a19# 67 i/o a20# 65 i/o a21# 66 i/o a22# 83 i/o a23# 64 i/o a24# 82 i/o a25# 46 i/o a26# 80 i/o a27# 81 i/o a28# 56 i/o a29# 94 i/o a30# 93 i/o a31# 79 i/o a32# 92 i/o a33# 91 i/o a34# 84 i/o a35# 97 i/o ad0 298 i/o ad1 295 i/o ad2 294 i/o ad3 290 i/o ad4 289 i/o ad5 287 i/o ad6 286 i/o ad7 285 i/o ad8 283 i/o ad9 281 i/o ad10 279 i/o ad11 278 i/o ad12 275 i/o ad13 274 i/o ad14 273 i/o ad15 271 i/o ad16 254 i/o ad17 253 i/o ad18 251 i/o ad19 250 i/o ad20 249 i/o ad21 247 i/o ad22 246 i/o ad23 243 i/o ad24 240 i/o ad25 239 i/o ad26 238 i/o ad27 236 i/o ad28 235 i/o ad29 234 i/o ad30 233 i/o ad31 231 i/o ads# 216 i/o aerr# 220 i/o ap0# 182 i/o ap1# 181 i/o bclk 175 i berr# 179 i/o binit# 214 i/o table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type bnr# 187 i/o bpri# 185 i/o c/be0# 282 i/o c/be1# 272 i/o c/be2# 255 i/o c/be3# 242 i/o creset# 105 o d0# 21 i/o d1# 23 i/o d2# 22 i/o d3# 31 i/o d4# 24 i/o d5# 33 i/o d6# 32 i/o d7# 34 i/o d8# 35 i/o d9# 48 i/o d10# 50 i/o d11# 59 i/o d12# 36 i/o d13# 60 i/o d14# 49 i/o d15# 51 i/o d16# 61 i/o d17# 62 i/o d18# 70 i/o d19# 71 i/o d20# 69 i/o d21# 72 i/o d22# 73 i/o d23# 74 i/o d24# 87 i/o d25# 86 i/o d26# 88 i/o d27# 89 i/o d28# 100 i/o table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type
a 82454kx/gx (pb) preliminary 81 d29# 98 i/o d30# 99 i/o d31# 101 i/o d32# 102 i/o d33# 111 i/o d34# 112 i/o d35# 109 i/o d36# 122 i/o d37# 117 i/o d38# 110 i/o d39# 123 i/o d40# 119 i/o d41# 131 i/o d42# 129 i/o d43# 120 i/o d44# 125 i/o d45# 126 i/o d46# 139 i/o d47# 128 i/o d48# 138 i/o d49# 136 i/o d50# 147 i/o d51# 132 i/o d52# 135 i/o d53# 145 i/o d54# 144 i/o d55# 155 i/o d56# 150 i/o d57# 142 i/o d58# 159 i/o d59# 141 i/o d60# 148 i/o d61# 157 i/o d62# 160 i/o d63# 156 i/o dbsy# 202 i/o table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type defer# 198 i/o dep0#/ 170 i/o gtlhi dep1#/ 166 i/o gtlhi dep2#/ 163 i/o gtlhi dep3#/ 173 i/o gtlhi dep4#/ 165 i/o gtlhi dep5#/ 169 i/o gtlhi dep6#/ 168 i/o gtlhi dep7#/ 162 i/o gtlhi devsel# 262 i/o drdy# 201 i/o flshbuf# 3 i flush# 178 o frame# 257 i/o gnd 1 v gnd 2 v gnd 13 v gnd 20 v gnd 25 v gnd 30 v gnd 39 v gnd 40 v gnd 47 v gnd 52 v gnd 58 v gnd 63 v gnd 68 v gnd 75 v table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type gnd 76 v gnd 85 v gnd 90 v gnd 95 v gnd 96 v gnd 103 v gnd 108 v gnd 115 v gnd 116 v gnd 118 v gnd 121 v gnd 124 v gnd 127 v gnd 130 v gnd 133 v gnd 134 v gnd 137 v gnd 140 v gnd 143 v gnd 146 v gnd 149 v gnd 153 v gnd 154 v gnd 158 v gnd 161 v gnd 164 v gnd 167 v gnd 172 v gnd 174 v gnd 176 v gnd 180 v gnd 183 v gnd 186 v gnd 191 v gnd 192 v gnd 197 v table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type
82454kx/gx (pb) a 82 preliminary gnd 200 v gnd 203 v gnd 206 v gnd 210 v gnd 215 v gnd 218 v gnd 221 v gnd 227 v gnd 228 v gnd 237 v gnd 244 v gnd 252 v gnd 260 v gnd 268 v gnd 276 v gnd 284 v gnd 293 v gtlvref 11 i hit# 207 i/o hitm# 204 i/o init# 208 o iognt#/ 297 i testhi ioreq#/ 296 i/o testlo irdy# 258 i/o lock# 205 i/o memack# 4 o memreq# 5 i pa r 2 7 0 i / o pcirst# 302 o pclk 226 i/o pclkin 225 i perr# 266 i/o pgnt# 224 i plock# 264 i/o table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type preq# 223 o ptrdy# 261 i/o pwrgd 6 i recven 9 i req0# 194 i/o req1# 193 i/o req2# 196 i/o req3# 195 i/o req4# 188 i/o reserved 104 nc reserved 106 nc reserved 107 nc reserved 241 nc reserved 265 nc reserved 291 nc reset# 177 i/o rp# 212 i/o rs0# 213 i/o rs1# 217 i/o rs2# 219 i/o rsp# 184 i/o serr# 267 o smiact# 211 o stop# 263 i/o tck 7 i tdi 12 i tdo 14 o testlo 300 i/o testlo 301 i/o tms 10 i trdy# 199 i/o trst# 8 i vcc3 19 v vcc3 37 v vcc3 38 v vcc3 57 v table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type vcc3 77 v vcc3 78 v vcc3 113 v vcc3 114 v vcc3 151 v vcc3 152 v vcc3 171 v vcc3 189 v vcc3 190 v vcc3 209 v vcc3 229 v vcc3 230 v vcc3 245 v vcc3 259 v vcc3 277 v vcc3 292 v vcc3 303 v vcc3 304 v vccpci 222 v vccpci 232 v vccpci 248 v vccpci 256 v vccpci 269 v vccpci 280 v vccpci 288 v vccpci 299 v table 13. 82454kx/gx pb alphabetical pin list (304-pin qfp) (continued) signal pin # type
preliminary 83 a 82454kx/gx (pb) figure 14. pb pin assignment (352 bga) 352bgapn.drw a b c d e f g h l m n p r t u v j k y w aa ab ac ad ae af a b c d e f g h l m n p r t u v j k y w aa ab a c a d ae af 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd gnd gnd gnd vccpci ad2 vccpci ad7 ad9 nc c/be1# vccpci plock# nc vccpci ad17 ad20 ad21 c/be3# ad26 ad29 ad31 gnd gnd gnd gnd gnd gnd gnd gnd gnd pcirst# ad1 ad4 vcc3 vcc3 vcc3 vcc3 vccpci ad12 perr# ptrdy# gnd nc ad23 ad28 ad30 gnd gnd gnd pclk gnd memreq# flshbuf# pwrgd gnd gnd pgnt# gnd preq# tms tck recven memack# pclkin vccpci rs1# rs2# tdi gtlvref gnd trst# gnd gnd aerr# rs0# a4# tdo a6# a3# binit# ads# init# smiact# d0# a10# d1# vcc3 vcc3 rp# lock# hit# d4# d2# a5# vcc3 vcc3 gnd gnd drdy# a7# a8# d3# nc hitm# dbsy# trdy# gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a9# d8# d5# nc defer# req0# req2# gnd gnd gnd gnd gnd gnd d7# d6# a13# gnd req4# req3# bnr# nc gnd gnd gnd gnd gnd gnd a17# d12# a14# nc gnd req1# nc bpri# gnd gnd gnd gnd gnd gnd a12# a11# gnd d14# rsp# gnd gnd ap1# gnd gnd gnd gnd gnd gnd d9# a25# d15# nc gnd ap0# reset# berr# ab3 gnd gnd gnd d21# d18# d55# d61# gnd gnd gnd gnd gnd a26# a34# a33# vcc3 vcc3 d31# d35# gnd nc d44# d47# vcc3 vcc3 d48# d57# d56# gnd gnd gnd gnd gnd gnd gnd gnd gnd a24# gnd d27# a30# d30# nc nc d33# gnd d43# d39# gnd gnd d49# d53# gnd d50# gnd gnd gnd gnd gnd gnd gnd gnd gnd a31# a22# d24# gnd a29# d29# d32# creset# gnd d34# d40# d36# d45# d42# d51# gnd d59# gnd gnd gnd gnd gnd gnd gnd gnd gnd a27# d25# d26# a32# a35# d28# nc nc d38# d37# nc nc d41# d52# d46# d54# d60# gnd gnd gnd gnd gnd a18# d10# a16# vcc3 vcc3 flush# gtlhi bclk a28# a15# d16# vcc3 vcc3 gnd gtlhi gtlhi d13# d11# a20# gnd gtlhi gtlhi nc gnd a23# d17# d20# a19# d62# gtlhi gtlhi gnd gnd a21# d19# d23# d63# gnd d58# gtlhi gnd gnd gnd gnd testlo testlo ad3 ad6 ad8 ad10 ad13 ad15 serr# devsel# frame# c/be2# ad18 vccpci ad25 nc nc nc gnd gnd gnd gnd gnd gnd gnd gnd testlo ad0 testhi nc ad5 c/be0# ad11 ad14 par nc stop# irdy# ad16 ad19 ad22 ad24 ad27 vccpci gnd gnd gnd gnd 82454gx a6 c7 u25 v25 v26 w23 w24 y24 y25 aa26 ioreq# iognt# dep3# dep5# dep0# dep1# dep6# dep4# dep2# dep7# 82454 pb bga n c = r e s e r v e d , m a k e n o c o n n e c t i o n
82454kx/gx (pb) a 84 preliminary table 14. 82454 kx/gx pb alphabetical ball list (352 bga) signal ball# type a3# h4 i/o a4# h1 i/o a5# k3 i/o a6# h3 i/o a7# l1 i/o a8# l2 i/o a9# m2 i/o a10# j2 i/o a11# r2 i/o a12# r1 i/o a13# n3 i/o a14# p3 i/o a15# v2 i/o a16# u3 i/o a17# p1 i/o a18# u1 i/o a19# y4 i/o a20# w3 i/o a21# aa2 i/o a22# ae6 i/o a23# y1 i/o a24# ad5 i/o a25# t2 i/o a26# ac6 i/o a27# af5 i/o a28# v1 i/o a29# ae9 i/o a30# ad8 i/o a31# ae5 i/o a32# af8 i/o a33# ac8 i/o a34# ac7 i/o a35# af9 i/o ad0 c6 i/o ad1 d7 i/o ad2 b6 i/o ad3 a7 i/o ad4 d8 i/o ad5 c9 i/o ad6 a8 i/o ad7 b8 i/o ad8 a9 i/o ad9 b9 i/o ad10 a10 i/o ad11 c11 i/o ad12 d12 i/o ad13 a11 i/o ad14 c12 i/o ad15 a12 i/o ad16 c17 i/o ad17 b16 i/o ad18 a17 i/o ad19 c18 i/o ad20 b17 i/o ad21 b18 i/o ad22 c19 i/o ad23 d19 i/o ad24 c20 i/o ad25 a20 i/o ad26 b20 i/o ad27 c21 i/o ad28 d20 i/o ad29 b21 i/o ad30 d21 i/o ad31 b22 i/o ads# h24 i/o aerr# g24 i/o ap0# t24 i/o ap1# r26 i/o bclk u26 i berr# t26 i/o binit# h23 i/o table 14. 82454 kx/gx pb alphabetical ball list (352 bga) (continued) signal ball# type bnr# n25 i/o bpri# p26 i/o c/be0# c10 i/o c/be1# b11 i/o c/be2# a16 i/o c/be3# b19 i/o creset# ae12 o d0# j1 i/o d1# j3 i/o d2# k2 i/o d3# l3 i/o d4# k1 i/o d5# m4 i/o d6# n2 i/o d7# n1 i/o d8# m3 i/o d9# t1 i/o d10# u2 i/o d11# w2 i/o d12# p2 i/o d13# w1 i/o d14# r4 i/o d15# t3 i/o d16# v3 i/o d17# y2 i/o d18# ab2 i/o d19# aa3 i/o d20# y3 i/o d21# ab1 i/o d22# ab3 i/o d23# aa4 i/o d24# ae7 i/o d25# af6 i/o d26# af7 i/o d27# ad7 i/o d28# af10 i/o table 14. 82454 kx/gx pb alphabetical ball list (352 bga) (continued) signal ball# type
a 82454kx/gx (pb) preliminary 85 d29# ae10 i/o d30# ad9 i/o d31# ac11 i/o d32# ae11 i/o d33# ad12 i/o d34# ae14 i/o d35# ac12 i/o d36# ae16 i/o d37# af14 i/o d38# af13 i/o d39# ad15 i/o d40# ae15 i/o d41# af18 i/o d42# ae18 i/o d43# ad14 i/o d44# ac15 i/o d45# ae17 i/o d46# af20 i/o d47# ac16 i/o d48# ac19 i/o d49# ad18 i/o d50# ad21 i/o d51# ae19 i/o d52# af19 i/o d53# ad20 i/o d54# af21 i/o d55# ab25 i/o d56# ac21 i/o d57# ac20 i/o d58# aa25 i/o d59# ae21 i/o d60# af22 i/o d61# ab26 i/o d62# y23 i/o d63# aa23 i/o dbsy# l24 i/o table 14. 82454 kx/gx pb alphabetical ball list (352 bga) (continued) signal ball# type defer# m24 i/o dep0#/ v26 i/o gtlhi dep1#/ w23 i/o gtlhi dep2#/ y25 i/o gtlhi dep3#/ u25 i/o gtlhi dep4#/ y24 i/o gtlhi dep5#/ v25 i/o gtlhi dep6#/ w24 i/o gtlhi dep7#/ aa26 i/o gtlhi devsel# a14 i/o drdy# k25 i/o flshbuf# e2 i flush# u24 o frame# a15 i/o gtlvref g2 i hit# j26 i/o hitm# l23 i/o init# h25 o iognt#/ c7 i testhi ioreq#/ a6 i/o testlo irdy# c16 i/o lock# j25 i/o memack# f4 o memreq# e1 i pa r c 1 3 i / o pcirst# d6 o table 14. 82454 kx/gx pb alphabetical ball list (352 bga) (continued) signal ball# type pclk d25 i/o pclkin f23 i perr# d13 i/o pgnt# e24 i plock# b13 i/o preq# e26 o ptrdy# d15 i/o pwrgd e3 i recven f3 i req0# m25 i/o req1# p24 i/o req2# m26 i/o req3# n24 i/o req4# n23 i/o reset# t25 i/o rp# j24 i/o rs0# g25 i/o rs1# f25 i/o rs2# f26 i/o rsp# r23 i/o serr# a13 o smiact# h26 o stop# c15 i/o tck f2 i tdi g1 i tdo h2 o testlo c5 i testlo a5 i tms f1 i trdy# l26 i/o trst# g4 i table 14. 82454 kx/gx pb alphabetical ball list (352 bga) (continued) signal ball# type
86 preliminary 82454kx/gx (pb) a notes: 1. for the bga package, external vcc 3 balls connect to a vcc 3 ring internal to the bga package, vcc 3 die pads are bonded to this ring. 2. for the bga package, the ground pins between brackets are thermal gnd pads under the die. external gnd balls connect to a gnd ring internal to the bga package, gnd die pads are bonded to this ring. 3. vcc 3 is the 3.3v supply. 4. vcc pci is the pci bus voltage. table 15. power, ground, and no connect (nc) signals (352, bga) signal bga ball # vcc 3 1,3 d9, d10, d17, d18, j4, k4, u4, v4, ac9, ac10, ac17, ac18, u23, v23, j23, k23 vcc pci 4 a18, b5, b7, b12, b15, c22, d11, f24 gnd 2 a1, a2, a3, a4, d14, b1, b2, b3, b4, e4, c1, c2, c3, c4, ac13, d1, d2, d3, d4, d5, n4, p23, a23, a24, a25, a26, b23, b24, b25, b26, c23, c24, c25, c26, d22, d23, d24, d26, e23, ac1, ac2, ac3, ac4, ac5, ab4, ad1, ad2, ad3, ad4, ae1, ae2, ae3, ae4, af1, af2, af3, af4, ac22, ac23, ac24, ac25, ac26, ab23, ad23, ad24, ad25, ad26, ae23, ae24, ae25, ae26, af23, af24, af25, af26, g3, m1, r3, w4, aa1, ad6, ae8, ae13, ad13, af15, ad16, ad17, ae20, ad19, ae22, ad22, ab24, aa24, y26, w26, v24, t23, r25, r24, l25, k26, k24, g26, g23, e25, [l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16] 2 nc, reserved l4, p4, t4, c8, b10, a19, a21, a22, b14, d16, c14, w25, p25, n26, m23, ad10, ac14, af16, af17, af11, af12, ad11
preliminary 87 a 82454kx/gx (pb) 4.2 package information figure 15. 82454kx/gx pb package physical dimensions (304-pin qfp) table 16. 82454kx/gx pb package physical dimensions (304-pin qfp) item millimeters inches item millimeter inches a 42.6 0.3 1.677 0.012 j 0.5 (t.p.) 0.020 (t.p.) b 40.0 0.2 1.575 0.008 k 1.3 0.2 0.051 0.008 c 40.0 0.2 1.575 0.008 l 0.5 0.2 0.020 0.008 d 42.6 0.3 1.677 0.012 m 0.125 0.05 0.005 0.002 f 1.25 0.049 n 0.10 0.004 g 1.25 0.049 p 3.7 0.146 h 0.20 0.10 0.008 0.004 q 0.4 0.1 0.016 .004 i 0.08 0.003 s 4.3 max 0.170 max top 304pin.drw a b 228 229 304 1 f g d c 76 77 153 152 m i n p k m enlarged detail of lead end q s 5 o l +/- 5 j h o
88 preliminary 82454kx/gx (pb) a figure 16. 82454kx/gx pb package physical dimensions (352 bga) top view 35.00 30.00 22.00 mold compound 1.27 bottom view pin one corner a b c d e f g h l m n p r t u v j k y w side view 352bgaor.drw 0.56 0.60 printed wire board mold compound die solder ball 30 typ. all sides 1.17 2.33 printed wire board 22.00 30.00 35.00 pin 1 corner aa ab ac ad ae af 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.27 1.27 1.63 1.63 1.27 o
preliminary 89 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) chapter 3 memory controller (mc) 82453kx/gx dram controller (dc) 82452kx/gx data path (dp) 82451kx/gx memory interface component (mic)
90 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a
a 82453kx/gx, 82452gx/kx, 82451kx/gx (mc) preliminary 91 memory controller (mc) 82453kx/gx dram controller (dc) 82452kx/gx memory data path (dp) 82451kx/gx memory interface component (mic) n 1 gb maximum main memory (450kx) n 2-way interleaved and non-interleaved memory organizations (450kx) n supports standard 32 or 36 bit simms n supports 72 bit dimms n 4 mbit, 16 mbit and 64 mbit dram n power management of memory array n recovers dram memory behind programmable memory gaps n available in 208-pin qfp for the dc; 240-pin qfp or 256-bga for the dp; 144- pin qfp for the mic n on-chip digital pll n jtag boundary scan support 4 gbytes maximum main memory (per 82453gx) 4-way, 2-way interleaved, and non- interleaved memory organizations (450GX) supports two mcs (450GX) system the mc consists of the 82453kx/gx dram controller (dc), the 82452kx/gx data path (dp), and four 82451kx/gx memory interface components (mic). the combined mc uses one physical load on the pentium pro processor bus. the memory configuration can be either non-interleaved (450kx/gx), 2-way interleaved (450kx/gx), or 4-way interleaved (450GX only). both single-sided and double-sided simms are supported at 3.3 and 5 volts. dram technologies of 512kx8, 1mx4, 2mx8, 4mx4, 8mx8, and 16mx4 at speeds of 50ns, 60ns, 70ns, and 80ns can be used. the maximum memory size is 4 gbytes for the 4-way interleaved configuration (450GX only), 1 gbyte (2 gbytes for the 450GX) for the 2-way interleaved configuration, and 512 mbytes (1 gbyte for the 450GX) for the non-interleaved configuration. the mc provides data integrity including ecc in the memory array, and parity on the host bus control signals. the 450GX also provides ecc on the host data bus. the mc is pc compatible. all isa and eisa regions are decoded and shadowed based on programmable configurations. regions above 1 mbyte with size 1 mbyte or larger that are not mapped to memory may be reclaimed. three programmable memory gaps can be created. for the 450GX, two mcs can be used in a system. the intel 450kx/gx pcisets may contain design defects or errors known as errata. current characterized errata are available upon request. n supports pentium a pro processor 60 mhz and 66 mhz bus speeds n supports 64-bit data bus and 36-bit address bus n parity protection on control signals n dual-processor support (450kx) n eight deep in-order queue n four deep outbound request queue n four cache line read buffer n four cache line write buffer n gtl+ bus driver technology n supports 3.3v and 5v simms n read access, page hit 8-1-1-1 (at 66 mhz, 60 ns dram) n read access, page miss 11-1-1-1 (at 66 mhz, 60 ns dram) n read access, page miss + precharge 14-1-1-1 (at 66 mhz, 60 ns dram) ecc on data bus (450GX) quad-processor support (450GX) this document describes both the 82454kx and 82454gx pcisets. unshaded areas describe features common to the 450kx and 450GX. shaded areas, like this one, describe the 450GX operations that differ from the 450kx.
92 preliminary 82453kx/gx, 82452gx/kx, 82451kx/gx (mc) a figure 1. memory controller (mc) simplified block diagram ads# req[4:0]# rp# a[35:3]# ap[1:0]# breq# aerr# bnr# hitm# hit# trdy# rsp# rs[2:0]# dbsy# berr# binit# reset# sbcerr# gtlrecv bclk pwrgd omcnum# dc memcmd[7:0]# memerr[1:0]# syscmd[4:0]# syserr# sysden# d[63:0]# dep[7:0]# drdy# gtlrefv bclk dp mirst# mirst# mde[17:0] mde[35:18] mde[53:36] mde[71:54] mic mde[71:0] mirst# mdrdy[1:0]# ixd[17:0] ixd[35:18] ixd[53:36] ixd[71:54] bclk micmwc[1:0]# miccmd[6:0]# maa[12:0] rasa[3:0]#,rasa[7:0]# casa[3:0]#,casa[7:0]# we0# mab[12:0] rasb[3:0]#,rasb[7:0]# casb[3:0]#,casb[7:0]# we1# memory interface x=interleave # x=0-1 (82450kx) x=0-3 (82450GX) shaded areas are 82450GX only
preliminary 93 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 1.0 mc signal description this section contains a detailed description of each signal. the signals are arranged in functional groups according to their interface. note that the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when # is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used extensively. this is done to avoid confusion when working with a mixture of active-low and active-high signals. the term assert , or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. the term negate , or negation indicates that a signal is inactive. the following notations are used to describe the signal type. i input is a standard input-only signal. o to t e m pole output is a standard active driver. i/o input/output is bi-directional, tri-state signal. gtl+ gtl+ processor bus signal defined for 1.5v operation. cmos rail-to-rail cmos tolerant to 5v levels. pci rail-to-rail cmos signal specifically for pci bus connection. analog reference voltage. 1.1 dc signals table 1. host bus address/control interface signals (dc) signal type description a[35:3]# i gtl+ address bus. upper address bits issued with the current request. ads# i gtl+ address strobe. ads# indicates that the current cycle is the first of two cycles of a request. aerr# i/o gtl+ address parity check. asserted when either an address or request parity error occurs. ap[1:0]# i gtl+ address parity. parity computed over the address; ap1# covers a[35:24]#, and ap0# covers a[23:3]#. berr# i/o gtl+ bus error. berr# indicates an unrecoverable bus error. bnr# i/o gtl+ block next request. bnr# is asserted by an agent to prevent the request bus owner from issuing further requests. breq0# o gtl+ bus request 0. asserted at reset to set agent ids in all processors. dbsy# i/o gtl+ data bus busy. dbsy# is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. hit# i/o gtl+ hit. indicates that a caching agent holds an unmodified version of the requested line. hit# is also driven in conjunction with hitm# to extend the snoop window.
94 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a . hitm# i/o gtl+ hit modified. hitm# indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. also, driven in conjunction with hit# to extend the snoop window. req[4:0]# i gtl+ request. in the first cycle of a request these signals carry the request type. in the second cycle they carry the data size and transfer length. rp# i gtl+ request parity. rp# is even parity that covers req[4:0]# and ads#. rp# is valid on both cycles of the request. rs[2:0]# i/o gtl+ response. rs[2:0]# encode the response to a request. rsp# i/o gtl+ response parity. rsp# provides response parity for rs[2:0]#. trdy# i/o gtl+ target ready. trdy# is driven by the target of the data to indicate it is ready to receive data. table 2. memory address/control interface signals (dc) signal type description casa[3:0]# casb[3:0]# o cmos column address strobe (two copies). indicates that the address on ma[12:0] is the column address. there is one cas# per logical row of memory. two copies are provided to support external loading. casa[7:0]# casb[7:0]# maa[12:0] mab[12:0] o cmos memory address (two copies). multiplexed row and column memory address. two copies are provided to support external loading. rasa[3:0]# rasb[3:0]# o cmos row address strobe (two copies). indicates that the address on ma[12:0] is the row address. there is one ras# per logical row of memory. two copies are provided to support external loading. rasa[7:0]# rasb[7:0]# we0# we1# o cmos write enable (two copies). indicates that the current memory request is a write. two copies are provided to support external loading. table 3. dc/dp interchip signals (dc) signal type description memcmd[7:0]# i/o cmos memory side command. these signals transfer command and configu- ration information between the dc and dp. memerr[1:0]# i cmos memory error. these signals transfer memory error information from the dp to the dc. table 1. host bus address/control interface signals (dc) (continued) signal type description
preliminary 95 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) syscmd[4:0]# o cmos system side command. these signals send commands and other information from the dc to the dp. sysden# o cmos system side data enable. this signal permits the dc to control the enabling of dp data information onto the host bus. syserr# i cmos system error. this signal sends system error data conditions from the dp to the dc. table 4. dc/mic interchip signals (dc) signal type description miccmd[6:0]# o cmos mic command. sends read/write/configuration commands to the mic. micmwc[1:0]# o cmos mic memory write command (two copies). instructs the mic to drive write data held in its internal buffers on the memory data bus. table 5. reset and error signals (dc) signal type description binit# i/o gtl+ bus initialization. binit# is asserted to initialize the host bus. configuration registers are not affected. mirst# o cmos memory interface reset. the dc uses this signal to reset the dp and mic. reset# i gtl+ reset. this is a hard reset to the dc. the dc sets its internal registers to their default conditions and asserts the mirst# to the dp and mics. sbcerr# o cmos single bit corrected error. when sbc error reporting is enabled in the merrcmd or serrcmd register, this signal is asserted to indicate that a single bit error was detected and corrected in the memory array. table 6. clock, power, and support signals (dc) signal type description bclk i cmos bus clock. this is the input clock for the dc. gtlrefv i analog gtl reference voltage. gtlrefv sets the voltage level used by the gtl input receivers for comparison against incoming gtl level signals. omcnum i cmos memory controller number. during a power-on reset, this signal provides the mc device number (see mcnum register). pwrgd i cmos power good. pwrgd is provided by the power supply when all voltages have stabilized for at least 1 ms. table 3. dc/dp interchip signals (dc) (continued) signal type description
96 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 1.2 dp signals . . table 7. test signals (dc) signal type description gtlhi i/o gtl+ these signals must be tied to v tt using a 10k w resistor for proper operation in both test and normal operating modes. tck i cmos jtag test clock. when tms is tied low, this signal has no effect on normal operation. tdi i cmos jtag test data in. when tms is tied low, this signal has no effect on normal operation. tdo o cmos jtag test data out. when tms is tied low, this signal has no effect on normal operation. testhi i/o test high. these signals must be tied high using a 10k w resistor for proper operation in both test and normal operating modes. testlo i/o test low. these signals must be tied low using a 1k w resistor for proper operation in both test and normal operating modes. tms i cmos jtag test mode select. this signal must be tied low for normal operation. trst# i cmos jtag test reset. when tms is tied low, this signal has no effect on normal operation. recven i receiver enable. this function is useful for component test. this signal is negated with pwrgood to disable gtl+ receivers and tri-state outputs for board test. table 8. host bus interface signals (dp) signal type description d[63:0]# i/o gtl+ data bus. the data bus consists of eight bytes. dep[7:0]# i/o gtl+ data ecc/parity. dep[7:0]# provides ecc for the d[63:0]# signals. ecc is computed over the 64 data bits. parity is not generated or checked by the mc. drdy# i/o gtl+ data ready. asserted for each cycle that data is transferred. table 9. data path interface signals (dp) signal type description mde[71:0] i/o cmos memory data and ecc. common to all types and sizes of memory supported, these signals include the 64 bits of data and 8 ecc check bits. ecc is computed over 64-bit data words. parity is computed as byte-parity over a 64-bit word. mdrdy0# mdrdy1# o cmos memory data ready (two copies). asserted when write data on the mde bus is valid. two copies are provided to support external loading.
preliminary 97 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) table 10. dc/dp interchip signals (dp) signal type description memcmd[7:0]# i/o cmos memory side command. these signals transfer command and configu- ration information between the dc and dp. memerr[1:0]# o cmos memory error. these signals transfer memory error information from the dp to the dc. syscmd[4:0]# i cmos system side command. these signals send commands and other information from the dc to the dp. sysden# i cmos system side data enable. this signal permits the dc to control the enabling of dp data information onto the host bus. syserr# o cmos system error. this signal sends system error data conditions from the dp to the dc. table 11. clock, power, reset signal (dp) signal type description bclk i cmos bus clock. this is the clock input for the dp. gtlrefv i analog gtl reference voltage. gtlrefv sets the voltage level used by the gtl input receivers for comparison against incoming gtl level signals. mirst# i cmos memory interface reset. this signal is driven by mirst# signal from the dc. table 12. test signals (dp) signal type description tck i cmos jtag test clock. when tms is tied low, this signal has no effect on normal operation. tdi i cmos jtag test data in. when tms is tied low, this signal has no effect on normal operation. tdo o cmos jtag test data out. when tms is tied low, this signal has no effect on normal operation. testhi i/o test high. these signals must be tied high using a 10k w resistor for proper operation in both test and normal operating modes. testlo i/o test low. these signals must be tied low using a 1k w resistor for proper operation in both test and normal operating modes. tms i cmos jtag test mode select. this signal must be tied low for normal operation. trst# i cmos jtag test reset. when tms is tied low, this signal has no effect on normal operation.
98 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 1.3 mic signals . table 13. control interface signals (mic) signal type description miccmd[6:0]# i cmos mic command. these signals send read/write/configuration commands to the mic. micmwc# i cmos mic memory write command. this signal instructs the mic to drive write data held in its internal buffers on the memory data bus. table 14. data path interface signals (mic) signal type description mde[17:0] i/o cmos memory data and ecc. mde[17:0] is one fourth of a qword and is connected to one of the word portions of the dp memory data bus. ecc is computed over 64-bit data words. mde[17:0] is one fourth of a qword. mdrdy# i cmos memory data ready. the dp asserts this signal to the mic when data on the mde bus is valid. table 15. memory interface signals (mic) signal type description i0d[17:0] i/o cmos memory data. i0d[17:0] is one fourth of a qword that is connected to interleave zero of the memory. i1d[17:0] i/o cmos memory data. i1d[17:0] is one fourth of a qword that is connected to interleave one of the memory. i2d[17:0] i/o cmos memory data. i2d[17:0] is one fourth of a qword that is connected to interleave two of the memory. i3d[17:0] i/o cmos memory data. i3d[17:0] is one fourth of a qword that is connected to interleave three of the memory. table 16. clock and reset signals (mic) signal type description bclk i cmos bus clock. this is the clock input to the device. mirst# i cmos memory interface reset. this signal is connected to the mirst# signal on the dc.
preliminary 99 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) . table 17. test signals (mic) signal type description tck i cmos jtag test clock. when tms is tied low, this signal has no effect on normal operation. tdi i cmos jtag test data in. when tms is tied low, this signal has no effect on normal operation. tdo o cmos jtag test data out. when tms is tied low, this signal has no effect on normal operation. testlo i/o test low. these signals must be tied low using a 1k w resistor for proper operation in both test and normal operating modes. tms i cmos jtag test mode select. this signal must be tied low for normal operation. trst# i cmos jtag test reset. when tms is tied low, this signal has no effect on normal operation.
82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 100 preliminary 1.4 signal state during reset table 18 shows the state of all mc output and bi- directional signals during a hard reset (reset# and mirst# asserted). table 18. signal state during reset signal state dc aerr# not driven bnr# not driven berr# not driven binit# not driven breq0# not driven casax# high casbx# high dbsy# not driven hit# not driven hitm# not driven maa[12:0] not driven mab[12:0] not driven memcmd[7:0]# high micccmd[6:0]# high micmwc[1:0]# high mirst# low rasax# high rasbx# high rs[2:0]# not driven rsp# not driven sbcerr# high syscmd[4:0]# high sysden# high tdo hi-z during trst# trdy# not driven wex# high dp d[63:0]# not driven dep[7:0]# not driven drdy# not driven mde[71:0] not driven mdmerr[1:0]# high mdrdy[1:0#] high memcmd[7:0]# high syserr# high tdo hi-z during trst# mic i0d[17:0] low i1d[17:0] low i2d[17:0] low i3d[17:0] low mde[71:0] low tdo hi-z during trst# table 18. signal state during reset (continued) signal state
preliminary 101 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.0 mc register description the mc contains two sets of registers (i/o space registers and configuration registers) that are accessed via the host cpu i/o address space. accessing mc configuration registers uses the same procedure as is defined for accessing pci device configuration registers (e.g., for the pb). the required pci header register set is provided permitting the mc to respond to initialization software in the same manner as an actual pci device (i.e., the mc register set is pci compliant). in some cases, (e.g., pcicmd register), the register may only be appropriate for a device attached to the pci bus. in these cases the register is shown as a read only register with the bits hardwired appropriately and writes have no effect. the i/o space registers (confadd and confdata registers) provide indirect access to the mc configu- ration registers. the mcs internal registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of confadd which can only be accessed as a dword. 0-length i/o reads are not supported by the mc. the following nomenclature is used for access attributes. ro read only. if a register is read only, writes to this register have no effect. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. some of the mc registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, unless otherwise specified in the individual register descriptions, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with new values for other bit positions and written back. in some cases, software must program reserved bit positions to a particular value. this value is defined in the individual bit descriptions. in addition to reserved bits within a register, the mc contains address locations in the mcs configuration space that are marked reserved. the mc responds to accesses to these address locations by completing the host transaction. software should not write to reserved mc configuration locations in the device-specific region (above address offset 3fh). 2.1 initialization and configuration after a power-on reset, the type of memory assumed is non-interleaved. the default dram timing values for the non-interleaved memory are set to reasonable values for 66 mhz and slow memory. it is expected that the bios will change these default memory timing values as necessary before memory is accessed. for the 450kx, the memory base address is hardwired to zero. for the 450GX, each mc memory base address is determined at reset according to its controller number (strapping option on the omcnum signal). after the power-on initialization, system bios determines memory size and configuration and programs the configu- ration registers accordingly. after a power-on reset, the mc is set for a 4 mbyte main memory size. the 512 kbyte dos ram region and accesses from 1 mbyte to 4 mbytes are enabled (mc accepts accesses). until initialized, the mc does not respond to any other memory locations. the mc and pb residing on the host bus contain a configuration space that is compliant with the configuration space in the pci bus specification. while the mc is not a true pci device, it uses the same configuration register access mechanism. the vid register (00C01h) and the did register (02C03h) both return legitimate values. the mc has two registers located in i/o spacethe configuration address (confadd) register and the configuration data (confdata) register. the compatibility pb is the only response agent for host accesses to confadd and the mc snoops writes to this register. confadd is first written to select the mc. a
102 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a subsequent read or write of confdata causes the mc to generate the requested configuration cycle on the host bus. during accesses to confdata, only the host device selected by confadd responds. if no valid device is selected in confadd, a subsequent confdata transaction is treated like a normal i/o transaction to i/o address cfch. the mc only snoops 32-bit writes to the confadd register. all other access sizes to the cf8h location are ignored by the mc. . 2.2 i/o space registers the mc has two registers located in i/o spacethe configuration address (confadd) register, and the configuration data (confdata) register. the confadd and confdata registers provide a window into the mcs configuration space registers. the specific device, and register are selected by writing to the confadd register. data is read from or written to the selected register by accessing the confdata register. note that the confadd register is only selected by dword accesses to cf8h. the confdata register is not selected unless configuration accesses are enabled in the confadd register. this allows the confdata register to overlap other registers. i/o address mnemonic register name access cf8h confadd configuration address wo cfch confdata configuration data r/w table 19. pci device numbers for bus number 0 device unique id loaded at reset pci device number pb 01 11001 pb 10 11010 mc 0 10100 mc 1 10101 reserved all other table 20. i/o space registers i/o address mnemonic register name access cf8h confadd configuration address r/w cfch confdata configuration data r/w there can be up to two mcs in the system. after power-on reset, the mc designated as controller number 0 (device number 10100 in the cdnum register) is the default response agent for accesses to the dos ram region (0C512 kbytes). the mc controller number is determined at reset by latching an id into the mc from the omcnum pin. both pbs default to bus number 0 after power-on reset. the mc is hard coded to bus number 0. each pb and mc must have a unique device number assigned at power-on reset. the relation between the pb and mc number and the device number that is assigned is shown in table 19.
preliminary 103 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.2.1 confaddconfiguration address register address offset: 0cf8h (dword access only) default: 00000000h attribute: write only the confadd register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. for example, a write of 8000a0ach to the confadd register can be used to access the 82453kx memory timing register. 2.2.2 confdataconfiguration data register address offset: 0cfch default: 00000000h attribute: read/write confdata is a 32-bit read/write window into configuration space. the portion of configuration space that is reference by confdata is determined by the contents of confadd. the be signals determine which bytes get written.. bits description 31 configuration enable (cse). 1=enable. 0=disable. 30:24 reserved. write 0s. 23:16 bus number (busnum). the mc bus number is 00h. 15:11 device number (devnum). the device number is reported in the cdnum register (offset 49h). 450kx: devnum=10100 (hardwired) 450GX: the device number for an mc is determined at power-up and is reported in the cdnum register (offset 49h). devnum=10100, or 10101 (depends on omcnum signal strapping). 10:8 function number (funcnum). the mc responds to configuration cycles with a function number of 000b. all other function number values attempting access to the mc (busnum=00h and devnum matching mc device number) are ignored by the mc. 7:2 register number (regnum). this field selects one register within mc, if the mc configuration space is selected by the other fields in the confadd register. 1:0 reserved. write 0s. bits description 31:0 configuration data window. if bit 31 of confadd=1, an access to confdata i/o space is mapped to configuration space using the contents of confadd.
104 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3 mc configuration registers table 21. mc configuration registers address offset mnemonic register name access 00C01h vid pci vendor identification ro 02C03h did pci device identification ro 04C05h pcicmd pci command ro 06C07h pcists pci status ro 08h rid revision identification ro 09C0bh classc class code ro 0cC3fh reserved 40C43h reserved (450kx) baseadd mc base address (450GX) r/w 44C48h reserved 49h cdnum controller device number ro 4aC4bh reserved 4cC4fh cmd mc command r/w 50C56h reserved 57h smme smram enable r/w 58h vbre video buffer region enable r/w 59C5fh pam[0:6] programmable attribute map (7 registers) r/w 60-63h drl[0:3] dram row limit for rows 0-3 r/w 64C67h reserved (450kx) drl[4:7] dram row limit for rows 4-7 (450GX) r/w 70C73h reserved 74C77h sbcerradd first single bit correctable error address r/w 78C79h mg memory gap register r/w 7aC7bh mgua memory gap upper address r/w 7cC7fh lmg low memory gap register r/w 80C87h reserved r/w 88C8bh hmgsa high memory gap start address r/w 8cC8fh hmgea high memory gap end address r/w 90Ca3h reserved a4Ca7h apicr i/o apic range register r/w
preliminary 105 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.1 vidvendor identification register address offset: 00C01h default: 8086h attribute: read only the vid register contains the vendor identification number. 2.3.2 diddevice identification register address offset: 02C03h default: 84c5h attribute: read only the did register contains the pci device identification. a8Cabh uerradd first uncorrectable error address ro acCafh memtim memory timing r/w b0Cb7h reserved b8Cbbh smmr smram range register r/w bch hbiosr high bios range register r/w bdCbfh reserved c0Cc1h merrcmd memory error reporting command register r/w c2Cc3h merrsts memory error status register r/w c4Cc5h serrcmd system error reporting command register r/w c6Cc7h serrsts system error status register r/w c8Cffh reserved bits description 15:0 pci vendor id. this 16-bit value (8086) is assigned to intel. bits description 15:0 pci device id. this 16-bit value (84c5) is assigned to the mc. table 21. mc configuration registers (continued) address offset mnemonic register name access
106 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.3 pcicmdpci command register address offset: 04C05h default: 0000h attribute: read only the pcicmd register controls the devices ability to respond to pci cycles. this register location is provided to maintain pci header register set compliance. 2.3.4 pcistspci status register address offset: 06C07h default: 0080h attribute: read only the pcists register reports various pci error conditions and indicates the devices response to various trans- actions on the pci bus. this register location is provided to maintain pci header register set compliance. 2.3.5 ridrevision identification register address offset: 08h default: see stepping information in the 450GX/kx specification update. attribute: read only this register contains the revision number of the mc. bits function 15:0 reserved. when read, this register returns 0000h. writes have no effect. bits function 15:0 reserved. when read, this register returns 0080h indicating that the mc is capable of fast back-to- back cycles. writes have no effect. bits function 7:0 revision identification value. this is an 8-bit value that indicates the revision identification number for the mc.
preliminary 107 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.6 classcclass code register address offset: 09C0bh default: 050000h attribute: read only this register contains the device programming interface information related to the sub-class code and base class code definition for the mc. this register also identifies the function sub-class in relation to the base class code and the based class code. 2.3.7 baseaddmc base address register (450GX only) bits description 23:16 base class code (bcc). 05h=memory controller device. 15:8 sub-class code (scc). 00h=ram device. 7:0 programming interface (pi). 00h=standard register format. bits description 31:16 reserved. 15:0 mc main memory base address (in units of 1 mbyte). bits [15:0] correspond to address bits a[35:20]#. address offset: 40C43h default: 0000 0000 0000 0000 000x 0000 0000 0000b (x=mc device number) attribute: read/write this register sets the base memory address for the mc. since there can be up to two mcs in a system, the default base address is determined at power-up (hard reset), assuming 4 gbytes of main memory behind each mc. the strapping option on the omcnum pin determines the mcs device number. this number affects a[33:32]# (bits[13:12]) of the default base address.
108 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.8 cdnumcontroller device number register address offset: 49h default: 00010100 (450kx) attribute: read only this register contains the mc device number. this value is hard coded in the 450kx. 2.3.9 cmdcommand register address offset: 4cC4fh default: 0000 0000 0000 0000 x000 1000 0000 1011b (x=captured from address bus on reset). attribute: read/write this register controls dram configuration, various memory controller operations, and reports the in-order queue depth. bits description 7:5 reserved. 4:1 fixed value. the upper four bits of the mc device number are always 1010 for the mc. 0 450kx: fixed value. the lower bit of the mc device number is always 0. 450GX: mc device number. the lower bit of the mc device number is encoded as follows: bits[1:0] function 0mc #0 1mc #1 bits description 31:16 reserved. 15 in-order queue depth 1 select. 1=depth of 1. 0=depth of 8. value captured from a7#. 14:11 active interleaves. 1=active. 0=inactive. each bit enables/disables a single interleave. for example, bits[14:11]=0101 defines a 2-way interleaved system with interleaves 2 and 0 active. default is bits[14:11]=0001. 0001010x (x=loaded at reset) this number is loaded from the omcnum pin. this pin must be strapped (vcc3 or gnd) appropriately. mc number 0 defaults to responding to dos accesses (0C512 kbytes). mc number 1 defaults to this range disabled (ignore these accesses). bit active interleave (450kx) 14 reserved 13 reserved 12 1 11 0 active interleave (450GX) 3 2 1 0 for a 4-way interleaved system that is functionally reduced to a non-interleaved or 2-way inter- leaved system, these bits define the currently active interleaves out of the four possible inter- leaves. for a 4-way interleave, all bits must be set to 1.
preliminary 109 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 10 page open policy. 1=hold page open. 0=close page (default). 9 common cas# enable. 1=enable (common cas# signals). 0=disable (independent cas# signals) (default). when enabled, this bit indicates when adjacent rows of memory have a common cas# connection. (this is typical of double-sided byte parity simms.) 8 extended read-around-write enable. 1=enable. 0=disable (default). when enabled, reads by- pass writes within the mics, provided their addresses do not match. note, this does not change the order in which data transfers occur on the host bus. this bit can not be enabled unless read- around-write is also enabled in bit 7. 7 read-around-write enable. 1=enable. 0=disable (default). when enabled, reads by-pass writes within the mc, provided their addresses do not match. note, this does not change the order in which data transfers occur on the host bus. 6 memory address bit permuting enable. 1=enable. 0=disable (default). when enabled, the mc permutes memory addresses to obtain alternate memory row selection bits. note that when enabled, there must be a power of 2 number of rows, all rows must be the same size, and all populated rows must be adjacent and start at row 0. 5 reserved. 4:3 memory configuration. the memory configuration is as follows: 2:0 read burst delay. this field selects the number of delay cycles between data qwords in a read burst. for a non-interleaved memory configuration, the number of delay cycles can be set to 3, 4, 5, or 6 clocks (read burst delay = (t rcas + t cp ) -1). for a 2-way interleaved configuration, the number of delay cycles can be set to 1, 2, or 3 clocks (read burst delay = ((t rcas + t cp )/2) - 1 and (t rcas + t cp ) must be even). for a 4-way interleaved configuration (450GX), the number of delay cycles must be set to 0 clocks. bits[2:0] delay cycles bits[2:0] delay cycles 000 0 (burst rate=1,1,1) 100 4 (burst rate=5,5,5) 001 1 (burst rate=2,2,2) 101 5 (burst rate=6,6,6) 010 2 (burst rate=3,3,3) 110 6 (burst rate=7,7,7) 011 3 (burst rate=4,4,4) (default) 111 7 (burst rate=8,8,8) bits description bit[4:3] function (450kx) 00 reserved 01 non-interleaved (default) 10 2-way interleaved 11 reserved function (450GX) reserved non-interleaved (default) 2-way interleaved 4-way interleaved
110 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.10 smmesmram enable register address offset: 57h default: 00h attribute: read/write this register enables/disables the smm range specified in the smmr register. 2.3.11 vbrevideo buffer region enable register address offset: 58h default: 00h attribute: read/write this register enables/disables the video buffer area. 2.3.12 pam[0:6]programmable attribute map registers address offset: pam0 (59h)pam6 (5fh) default: pam0=03h, pam[1:6]=00h attribute: read/write these seven registers select read only (re=1, we=0), write only (re=0, we=1), or read/write (re=1, we=1) access attributes for 14 memory regions between the 512 kbyte and 1 mbyte address range. the individual memory regions can also be disabled (re=0, we=0). each register controls two regions; bits [7:4] control one region and bits [3:0] control the other region. note that the default for the 512C640 kbyte region is read/write enabled. the default for all other regions is read/write disabled. note that the pb has corresponding pam registers. only one device (mc/pb) should have the same space enabled at one time to avoid access conflicts read enable (re) when re=1 (enabled), cpu read accesses to the corresponding memory region are directed to main memory. when re=0 (disabled), cpu read accesses are ignored. write enable (we) when we=1 (enabled), cpu write accesses to the corresponding memory region are directed to main memory. when we=0 (disabled), cpu write accesses are ignored. bits description 7:4 reserved. 3 smm ram enable. 1=enable. 0=disable. 2:0 reserved. bits description 7:2 reserved. 1 video buffer area enable (a0000Cbffffh). 1=enable. 0=disable. 0 reserved.
preliminary 111 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.13 drldram row limit (0 to 7) address offset: 60C6fh default: 0001h attribute: read/write the 450kx mc supports 4 rows of dram. drl[0:3] define the upper and lower addresses for each dram row. the addresses are relative to the memory space of the mc and do not include any programmed memory gaps. the contents of these 16-bit registers represent the boundary addresses in 4 mbyte granularity. rows with no memory are programmed with the upper limit of the previous row. the default after reset reflects the requirement that the first row be populated. note that for the 450kx, drl[4:7] must be programmed with the value programmed in drl3. drl0 = total memory in row 0 (in 4 mb) drl1 = total memory in row 0 + row 1 (in 4 mb) drl2 = total memory in row 0 + row 1 + row 2 (in 4 mb) drl3 = total memory in row 0 + row 1 + row 2 + row 3 (in 4 mb) pam attribute bits memory segment comments offset register 7,3 6,2 5,1 4,0 pam0[7:4] reserved we re 0f0000C0fffffh bios 59h pam0[3:0] reserved we re 080000C09ffffh 512C640 kb 59h pam1[7:4] reserved we re 0c4000C0c7fffh isa expansion 5ah pam1[3:0] reserved we re 0c0000C0c3fffh isa expansion 5ah pam2[7:4] reserved we re 0cc000C0cffffh isa expansion 5bh pam2[3:0] reserved we re 0c8000C0cbfffh isa expansion 5bh pam3[7:4] reserved we re 0d4000C0d7fffh isa expansion 5ch pam3[3:0] reserved we re 0d0000C0d3fffh isa expansion 5ch pam4[7:4] reserved we re 0dc000C0dffffh isa expansion 5dh pam4[3:0] reserved we re 0d8000C0dbfffh isa expansion 5dh pam5[7:4] reserved we re 0e4000C0e7fffh bios extension 5eh pam5[3:0] reserved we re 0e0000C0e3fffh bios extension 5eh pam6[7:4] reserved we re 0ec000Ceffffh bios extension 5fh pam6[3:0] reserved we re 0e8000C0ebfffh bios extension 5fh the 450GX supports 8 rows of dram. drl[0:7] define the upper and lower addresses for each dram row. drl4 = total memory in row 0 + row 1 + row 2 + row 3 +row 4 (in 4 mb) drl5 = total memory in row 0 + row 1 + row 2 + row 3 +row 4 +row 5 (in 4 mb) drl6 = total memory in row 0 + row 1 + row 2 + row 3 +row 4 +row 5 + row 6 (in 4 mb) drl7 = total memory in row 0 + row 1 + row 2 + row 3 +row 4 +row 5 + row 6 +row 7 (in 4 mb)
112 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.14 sbcerraddsingle bit correctable error address register address offset: 74C77h default: 0000h attribute: read only this register provides the effective address of the memory access that caused a single bit correctable error on the memory side. the value in this register is only valid if the sbc correctable error bit is set in the merrsts register (c2Cc3h). bits description 15:7 reserved. 6:0 dram row upper address limit (in units of 4 mbytes). this 7-bit field determines the upper address limit of a particular row (i.e., drl minus previous drl = row size). note that the allowed minimum and maximum values for row size depend on the memory configuration (non-interleaved row size = 4 mbytes minimum and 128 mbytes maximum; 2-way interleaved row size = 8 mbytes minimum and 256 mbytes maximum). example: row 0 has 16 mbytes, row 1 is unpopulated, and row 2 has 32 mbytes. the drl registers would be programmed as follows: drl0 = 04h drl1 = 04h drl[2:7]= 0ch (each register) bits description 15:11 reserved. 10:0 dram row upper address limit (in units of 4 mbytes). this 11-bit field determines the upper address limit of a particular row (i.e., drl minus previous drl = row size). note that the allowed minimum and maximum values for row size depend on the memory configuration (non-interleaved row size = 4 mbytes minimum and 128 mbytes maximum; 2-way interleaved row size = 8 mbytes minimum and 256 mbytes maximum; 4-way interleaved = 16 mbytes minimum and 512 mbytes maximum). example: in a 4-way interleaved configuration with all rows containing 512 mbytes, the drl registers would be programmed as follows: drl0 = 80h drl4 = 280h drl1 = 100h drl5 = 300h drl2 = 180h drl6 = 380h drl3 = 200h drl7 = 400h
preliminary 113 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.15 mgmemory gap register address offset: 78C79h default: 0010h attribute: read/write this register, along with the mgua register, defines the memory gap. note that the memory gap must be located above the low memory gap and below the high memory gap. bits description 31:3 address of first single-bit correctable ecc error. this is the effective dram address used in the mc and must be converted back to the original physical address by software. the programmed memory gaps and mc base address must be taken into account for proper calculation of the address in which the dram side ecc error occurred. 2:1 qword number error detect. when a single-bit error occurred in a transfer from the dram array, this field indicates which qword in the transfer contained the error. note that this field reports the qword number relative to the order of the transfer (0 to 3), even if the transfer does not begin with the first qword of a cache line. in addition, in a single qword transfer, if an error is detected, this field will be set to 00. for further granularity in determining the address of the error, bit 0 of this register reports which half of the qword contained the error. bits [2:1] qword number of the transfer 00 first qword transferred (qword 0) 01 second qword transferred (qword 1) 10 third qword transferred (qword 2) 11 fourth qword transferred (qword 3) 0 dword number error detect (in a qword). 1=error in upper dword. 0=error in lower dword. when a single-bit error occurred in a transfer from the dram array, this bit identifies which half of the qword (upper 2 words or lower 2 words) contains the error. single-bit error correcting of memory data must enabled (bit 2 of merrcmd register, c0Cc1h) to obtain this functionality. bits description 15 memory gap enable. 1=enable. 0=disable (default). 14:10 memory gap size. this field defines the memory gap size as follows: bits[14:10] size bits[14:10] size 00000 1 mb 11100 8 mb 00100 2 mb 11110 16 mb 01100 4 mb 11111 32 mb note that all other combinations are reserved. 9 reclaim enable. 1=enable. 0=disable (default). when enabled, the physical memory in this gap is reclaimed. 8 reserved. 7:4 memory gap starting address (lower nibble). bits [7:4] correspond to a[23:20]# and are used with bits [11:0] of the mgrua register to form the complete starting address. 3:0 reserved.
114 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.16 mguamemory gap upper address register address offset: 7aC7bh default: 0000h attribute: read/write this register is used, along with the mg register, to define the memory gap. 2.3.17 lmglow memory gap register address offset: 7cC7fh default: 00100000h attribute: read/write this register defines the low memory gap range. note that the low memory gap must be located below the memory gap and the high memory gap. bits description 15:12 reserved. 11:0 memory gap starting address (upper part). these bits correspond to address bits a[35:24]# and are used with bits [7:4] of the mg register to form the complete starting address. bits description 31:20 low memory gap starting address (in 1 mbyte increments) . bits [31:20] correspond to address bits a[31:20]#. a[35:32]# are zero for this range (i.e., this range is limited to the lower 4 gbytes). 19:12 reserved . 11 low memory gap enable. 1=enable. 0=disable (default). 10 reclaim enable. 1=enable. 0=disable (default). when enabled, the physical memory in this gap is reclaimed. 4:0 low memory gap size. this field defines the memory gap size as follows: bits[4:0] size bits[4:0] size 00000 1 mb 11100 8 mb 00100 2 mb 11110 16 mb 01100 4 mb 11111 32 mb note that all other combinations reserved.
preliminary 115 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.18 hmgsahigh memory gap start address register address offset: 88C8bh default: 0000h attribute: read/write this register, along with the hmgea register, define the high memory gap. 2.3.19 hmgeahigh memory gap end address register address offset: 8cC8fh default: 0000h attribute: read/write this register, along with the hmgsa register, define the high memory gap. 2.3.20 apicri/o apic range register address offset: a4Ca7h default: 00fec001h attribute: read/write this register defines a 64 kbyte i/o apic range. bits description 31 high memory gap enable . 1=enable. 0=disable (default). 29:16 reserved. 15:0 high memory gap start address (in 1 mbyte increments). bits[15:0] correspond to a[35:20]#. bits description 31:16 reserved. 15:0 high memory range end address (in 1 mbyte increments). bits[15:0] correspond to a[35:20]# of the last 1 mbyte region within the memory gap. bits description 31:28 reserved. must be set to zero. 27:12 i/o apic base address (located on 1 mb increments). bits[27:12] correspond to a[35:20]#. 11:4 reserved. used in pb for unit id numbers. 3:1 reserved. 0 i/o apic range enable. 1=enable (default). 0=disable. the i/o apic range is 64 kbytes. when this region is enabled, accesses to the region are ignored by the mc.
116 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.21 uerradduncorrectable error address register address offset: a8Cabh default: 0000h attribute: read only this register provides the effective address of the memory access that caused an uncorrectable ecc error. the value in this register is only valid if the sbc error bit is set in the error reporting register. 2.3.22 memtimmemory timing register address offset: acCafh default: 30df3516h attribute: read/write the memory timing register has two main functional sectionsrefresh timing and memory timing. the refresh timing portion of the memory timing register includes selections for time between refreshes (refresh counter) and time between refreshing rows in the memory array (refresh stagger). an enable bit for refreshing is also provided. most of the asynchronous dram timing parameters are programmable in the mc to achieve maximum perfor- mance across a wide range of system operating frequencies. each field in the memory timing register that pertains to dram timing is referenced by the most common dram timing parameter as published in the major dram vendors data books. each field provides enough values to cover a wide range of operating frequencies. care must be taken in programming the memory timing parameters so that the proper system timing is achieved and no conflicts are induced. the memory timing register allows the memory controller to be adjusted for maximum performance when accessing asynchronous drams. the mc generates all control signals synchronously to the system clock. this limits the granularity of the generated control signals to a single clock period. the memory timing register allows the selection of the number of clocks to the most optimal value for a wide range of system clock frequencies. bits description 31:3 address of first uncorrectable ecc error. this is the effective address used in the mc and must be converted to the original physical address by software. mc base address and any programmed memory gaps must be taken into account for proper calculation of the address. 2:1 qword number error detect. when an uncorrectable error occurred in a transfer, this field indicates which qword in the transfer contained the error. note that this field reports the qword number relative to the order of the transfer (0 to 3), even if the transfer does not begin with the first qword of a cache line. in addition, in a single qword transfer, if an error is detected, this field will be set to 00. bits [2:1] qword number of the transfer 00 first qword transferred (qword 0) 01 second qword transferred (qword 1) 10 third qword transferred (qword 2) 11 fourth qword transferred (qword 3) 0 reserved.
preliminary 117 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) on reset, the memory timing register fields are set to values that allow operation in the range 50 mhz to 66 mhz with 70 ns drams. the refresh counter is set such that refreshes occur assuming that the operating frequency is 50 mhz, which is faster than required at 60 or 66 mhz. all other parameters are set assuming that the operating frequency is 66 mhz which adds more clocks than required if the real frequency is 60 mhz. for optimal performance, the values in this register may have to be reprogrammed after reset. bits description 31 reserved. 30:20 refresh count (in cycles) (refrc). the refresh counter must be set so that refreshes occur often enough that the entire dram array is refreshed before dram data loss occurs. the eleven bit counter can be programmed from 1 to 2047. the counter time base is equal to one system clock period (15 ns for a 66 mhz clock, etc.). the value is chosen to give a refresh every 15.625 usec (or less). for example, 30dh=15.620 usec at 50 mhz (default) and 411h = 15.615 usec at 66 mhz 19:17 refresh stagger (refrs). the refresh stagger sets the time, in clock cycles, from the start of one rows refresh to the start of the next rows refresh. refresh in the drams causes the drams to become active which draws considerable power. refreshing all rows at once may not be possible for the system power supply. the refresh stagger field of the memory timing register allows the power surge to be spread evenly across the refresh cycle. the amount of time necessary to stagger the refreshes is system design and dram memory type dependent. 000=all rows refreshed at once. bits[19:17] stagger bits[19:17] stagger 000 0 cycles 100 4 cycles 001 1 cycle 101 5 cycles 010 2 cycles 110 6 cycles 011 3 cycles 111 7 cycles (default) 16 refresh enable (refre). 1=enable (default). 0=disable. 15 cas# setup time to ras# for cas-before-ras refresh cycles. 1=1 cycles. 0=2 cycle (default). typically, 1 cycle is sufficient. however, in some cases the combination of dram timings, clock speed, and system level skew between casx# and rasx# may require 2 cycles. 14:13 last write to cas# (lwc). number of cycles from when the last data is asserted to the mic to when cas# is asserted. this determines data setup time before cas# (i.e., data is driven for lwc cycles, but delayed by one cycle). bits[14:13] cycles 00 reserved 01 2 (default) 10 3 11 4 notes: 1. write data setup time to cas# asserted is lwc minus 1. 2. write data hold time from cas# asserted is 1 cycle if wcas (bits[7:6]) equals 2 and is 2 cycles if wcas is greater than 2. 3. the following are the legal combinations of the wcas, lwc, and cp fields for non-interleaved and 2-way interleaved memory configurations. there are no restrictions for 4-way interleaved. wcas lwc cp wcas lwc cp 221,2 4 21,2 232 4 31,2 321,2 4 42 332
118 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 12:11 ras# pulse width (raspw). this field selects the minimum cycles that rasx# is asserted. raspw should be set to the larger of the following values(rcd + cah + 1) or (rcd + wcas - 1) or (rcd +rcas - 1) bits[12:11] cycles 00 4 01 5 10 6 (default) 11 7 10 column address hold time (cah). 0=1 cycle. 1=2 cycles (default). cah is the number of cycles from the time cas# is asserted to when the column address can be changed. note that cah must be set to 1 cycle if rcas=2 or raspw minus rcd = 2. 9:8 read cas# pulse width (rcas). number of cycles cas# is asserted for read cycles. rcas must be set to ensure data setup to the dp from cas# asserted. bits[9:8] cycles 00 2 01 3 (default) 10 4 11 5 7:6 write cas# pulse width (wcas). wcas selects the number of cycles cas# is asserted for write cycles. see notes for lwc field description. wcas should be set to rcas or rcas minus 1, depending on data hold time requirements (see lwc field). bits[7:6] cycles 00 2 (default) 01 3 10 4 11 5 5 cas# precharge time (cp). 0=1 cycle (default). 1=2 cycles. cp selects the number of cycles for cas# precharge. see notes for lwc field description. 4 ras# to column address delay (rcad). rcad selects the number of cycles from the time ras# is asserted to when column address is asserted. 0 = 1 cycle. 1 = 2 cycles (default). rcad must equal 1 cycle if rcd equals 2 cycles. 3:2 ras# to cas# delay (rcd). rcd selects the number of cycles from the time ras# is asserted to when cas# is asserted. bits[3:2] cycles 00 reserved 01 3 (default) 10 4 11 reserved 1:0 ras# precharge time (rp). rp selects the number of cycles for ras# pre-charge. bits[1:0] cycles 00 3 01 4 10 5 (default) 11 6 bits description
preliminary 119 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.23 smmrsmram range register address offset: b8Cbbh default: 000ah attribute: read/write this register controls the size and location of smram. 2.3.24 hbiosrhigh bios gap range register address offset: bch default: 01h attribute: read/write this register enables/disables the high bios range. this range is 2 mbytes extending from 00_ffe0_0000h to 00_ffff_ffffh). bits description 31:28 smm range size. the size (in 64 kbyte increments) is selected as follows: bits[31:28] size bits[31:28] size 0000 64 kb (default) 0100 512 kb 0001 128 kb ... ... 0010 192 kb 1111 1 mb 0011 256 kb 27:16 reserved. 15:0 smm range start address (in 64 kbyte increments). bits [15:0] correspond to a[31:16]#. default=a0000. bits description 7:1 reserved. 0 high bios range enable. 1=enable (default). 0=disable. when enabled, the mc ignores accesses to this range.
120 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.25 merrcmdmemory error reporting command address offset: c0Cc1h default: 0000h attribute: read /write this register enables/disables the correcting of single bit errors in memory data. this register also controls the reporting of correctable and uncorrectable memory errors. 2.3.26 merrstsmemory error status register address offset: c2Cc3h default: 0000h attribute: read /write clear this register logs correctable and uncorrectable memory errors. software sets these bits to 0 by writing a 1 to them. bits description 15:3 reserved. 2 single-bit error correcting of memory data enable. 1=enable. 0=disable (default). this bit must be enabled for the identify simm functionality described for bit 0 in the sbcerradd register (detecting which half of a qword generated the error). 1 report correctable memory errors enable. 1=enable. 0=disable (default). when enabled, the mc reports correctable errors in data read from memory in the merrsts register. the mc also asserts the sideband single sbcerr#. 0 report uncorrectable memory errors enable. 1=enable. 0=disable (default). when enabled, the mc logs uncorrectable errors in the mc memory error status register. if berr# output is enabled (serrcmd register), berr# is also be asserted. bits description 15:2 reserved. 1 correctable memory error. 1=detected correctable memory error. 0 uncorrectable memory error. 1=detected uncorrectable memory error.
preliminary 121 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 2.3.27 serrcmdsystem error reporting command register address offset: c4Cc5h default: 0000_0000_000x_0x0xb (x=captured at reset) attribute: read/write this register controls the reporting of system errors. note that when bits[9:7] of this register are disabled, the mc forces all ecc bits written to memory to 0. this mechanism is used to force ecc errors in the memory array for debugging the memory error correcting/detecting circuits. bits description 15:10 reserved. 9 450kx: reserved. 8 450kx: reserved. 7 450kx: enable memory ecc. 1=enable. 0=disable. this bit must be set to enable ecc on the memory array. the memory array must be initialized before enabling memory ecc. 6 reserved. 5 aerr# driver enable. 1=enable. 0=disable (default). this bit enables/disables reporting of parity errors on request signals. 4 aerr# input enable. 1=enable. 0=disable. the mc captures this value from a8#. 3 berr# driver enable. 1=enable. 0=disable (default). this enables/disables reporting of uncor- rectable errors on the data bus or memory interface. 2 berr# input enable. 1=enable. 0=disable. the mc captures this value from a9#. 1 binit# driver enable. 1=enable. 0=disable. when enabled, protocol violations are reported on binit#. 0 binit# input enable. 1=enable. 0=disable. the mc captures this value from a10#. 450GX: single-bit error correcting of host data enable. 1=enable. 0=disable (default). 450GX: logging correctable errors on the host data bus enable. 1=enable. 0=disable (default). when enabled, the mc logs correctable errors in data read from the host bus in the serrsts register. the mc also asserts the sideband single sbcerr#. 450GX: logging uncorrectable errors on the host data bus enable. 1=enable. 0=disable (default). when enabled, the mc logs uncorrectable errors in the serrsts register. if berr# is enabled, berr# is also be asserted. the memory array must be initialized before enabling memory ecc.
122 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 2.3.28 serrstssystem error status register address offset: c6Cc7h default: 0000h attribute: read /write clear this register logs system errors. software sets these bits to 0 by writing a 1 to them. 2.4 memory configuration determination algorithm the number of rows of memory and the size of the memory in each row must be determined by power-on self test (post) code prior to programming the configuration registers for the true system configuration. after reset, each mc is configured for a non-interleaved memory configuration operating with the default values given in the memory timing register. base addresses are set assuming maximum memory. however, row limits are set at 4 mbytes. to complete the configuration of the mcs in a system the bios must perform a complete setup as described in the pentium pro processor bios writers guide (order #649733). bits function 15:5 reserved. 4 host address parity error detected. (via ap[1:0]#). 1=logs parity errors on a[35:3], regardless of whether the event is reported. if aerr# input enable (bit 4) of the serrcmd register is set, the event is reported during the error phase. 3 host bus request parity error detected (via rp#). 1=logs parity errors on the ads# and req[4:0]# signals, regardless of whether the event is reported. if enabled in the serrcmd register (bit 4), this error is reported by generating an aerr#. 2 450kx: reserved. 1 450kx: reserved. 0 host bus protocol violation detected (via rsp#). 1=logs protocol violations, regardless of whether event is reported. if binit# is enabled in the serrcmd register, these errors are reported by generating a binit#. 450GX: host bus correctable error detected. 1=logs a single-bit ecc error detected on the host data bus. no error is reported when a host bus correctable error is detected. 450GX: host bus uncorrectable error detected. 1=logs a multiple-bit ecc error detected on the host data bus. note that this bit is set independent of whether error reporting is enabled via bit 7 of the serrcmd register. if berr# is enabled in the serrcmd register, this error is reported by generating a berr#.
preliminary 123 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 3.0 mc functional description this section describes the mc functions and hardware interfaces including the memory and i/o mapping, host bus interface, dram interface, and clocks and reset. 3.1 memory and i/o map the mc provides the interface between the host bus and main memory. the processor memory space is 64 gbytes (36-bit addressing). an mc can control up to 1 gbyte of memory for the 450kx and 4 gbytes of memory for the 450GX. the mc registers that control memory space access are: ? programmable attribute map (pam[6:0]) registers. these registers provide read only, write only, and read/write disable for fixed memory regions in the pc compatibility area. ? video buffer area enable (vba) register. this register enables the a0000Cbffffh fixed region. ? low memory gap (lmg) register. this register defines a hole in memory located from 1 to 4 gbytes on any 1 mbyte boundary where accesses can be directed to the pci bus (via the pb). the size can be 1, 2, 4, 8, 16, or 32 mbytes. this gap must be located below the memory gap and high memory gap. the low memory gap is used by isa devices such as lan or linear frame buffers that are mapped into the isa extended region, or by any eisa or pci device. ? memory gap registers (mg and mgua) registers. these two registers define a hole in memory located from 1 to 64 gbytes on any 1 mbyte boundary where accesses can be directed to the pci bus (via the pb). this gap (1, 2, 4, 8,16, or 32 mbytes in size) must be located above the low memory gap and below the high memory gap areas. the memory gap is used by isa devices (e.g., lan or linear frame buffers) that are mapped into the isa extended region, or by any eisa or pci device. ? high memory gap registers (hmgsa and hmgea) registers. these two registers define a gap in memory that can be located from 1 to 64 gbytes on any 1 mbyte boundary where accesses can be directed to the pci bus (via the pb). the size ranges from 1 mbyte to 64 gbytes. this gap must be located above the memory gap and the low memory gap areas. the high memory gap provides additional support for memory mapped i/o. ? smmram range (smmr) register and the smmram enable (smme) register (only when smmem# is asserted by the processor.). sm memory can overlap with memory residing on the host bus or memory normally residing on the pci bus. when the sm range is enabled, sm accesses are handled by the mc. if the smmem# signal is not asserted, accesses to the mcs enabled sm range are ignored (this allows the sm memory to overlap with memory normally residing on the host bus, since the smm range may also be mapped through another mc range register). the rsmi# signal may be asserted in the response phase by a device in smm power-down mode. the mc does not assert this signal. note: since leaving system management mode effectively remaps the system memory space, one must take care with smm memory that is cached. if smmram is cast as writeback memory, a wbinvd instruction must be executed immediately prior to the execution of the rsm instruction which exits smm mode. this will force all modified data to be written back while memory is still mapped for smm. ? base address (baseadd) register. an 82453gx responds to memory accesses between the address programmed into this register and the calculated top of its memory range (calculated top of mc memory address = base + memory size + low memory gap size + memory gap size + high memory gap size). note that the dram memory behind the memory gaps can be reclaimed.
124 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a ? high bios (hbios) register. the 64 kbyte region from f0000Cfffffh is treated as a single block and is normally read/write disabled in the mc(s) and read/write enabled in the pb. after power-on reset, this region is r/w enabled in the pb (compatibility pb only in the 450GX and r/w disabled in the auxiliary pb). thus, the pb can respond to fetches during system initialization. the read/write attributes for this region may be used in conjunction with the read/write attributes in the pb to shadow bios into ram. ? i/o apic range (apicr) register. this register provides an i/o apic configuration space. there is no i/o apic in the pb or the mc. ? dram row limit (drl) registers. these registers define the upper and lower addresses for each dram row and represent the boundary addresses in 4 mbyte granularity. if a memory space access is in one of the above ranges, and that range is enabled for memory access, the mc claims the transaction and becomes the response agent. the mc performs memory recovery on gap ranges greater than or equal to 1 mbyte that are created by the low memory gap, memory gap, and the high memory gap areas. this memory is relocated to the top of the mcs memory. the mc performs a subtraction of the size of the hole in the memory map to generate an effective memory address. note that the pb (compatibility pb in an 450GX dual pb system) is responsible for claiming any unclaimed transactions on the host system bus. therefore, any memory space access that is above the top of system main memory is claimed by the pb. the mc has two registers located in the processors i/o space (0cf8h and 0cfch) that are used to configure the mc. see the register descripiton section for details. 3.2 host bus interface the pentium pro processor bus provides an efficient, reliable interconnect between multiple pentium pro processors and the pb and mc. the bus provides 36 bits of address, 64 bits of data, protection signals needed to support data integrity, and the control signals to maintain a coherent shared memory in the presence of multiple caches. the pentium pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans- actions and deferred replies. a single pentium pro processor may have up to four transactions outstanding at the same time, and can be configured to support up to eight transactions active on the pentium pro processor bus at any one time. the mc supports up to four transactions that target its associated memory space. the mc contains read and write buffers for memory accesses. for the 450GX, the base address for the mc that is not mc #0 must include the size of any memory gaps programmed in the previous (or lower base address) mc. there can be up to two mcs in a system permitting up to 8 gbytes of system main memory. the portion of the processors memory space controlled by an mc is determined by the base address register and memory size. in a pc architecture, the only restrictions on mc placement are that there be memory starting at address 0 and that there be enough memory to operate a system. the mcs in a system need not have contiguous address spaces. the high memory gap in one mc could be used to span the gap between the top of its memory map and the base address of the other mc.
preliminary 125 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) notes: 1. the mc does not generate deferred responses. 2. the mc does not provide the ability to abort a transaction during the response phase. 3. on the host bus, a hard failure response is generated for failures in accessing a resource. such a failure could be a time-out after requesting a device that is not available. note that data failures do not fall into a hard failure class. the mc does not generate hard failure responses. 4. all transactions in the mc are processed in address order with respect to when they are received on the host bus. there is reordering of read-around-writes, but only when the address of the read is different from the address of the write. if there is an address conflict, the transactions are processed in the order they are received. (note, responses to transactions still occur in the order in which they were received, only the processing of the requests is reordered.) 5. the mc does not respond to an smi acknowledge transaction or stop clock acknowledge transaction, even though they are encoded as memory type operations on the host bus. aerr#. an aerr# on the host bus stops traffic in the memory controller. reporting is done by the 82454 (pb). binit#. a binit# on the host bus resets the 450kx/gx host bus state machines. this allows for logging or recovery from catastrophic bus errors. note that during the last clock of a binit# pulse, ads# may not be asserted as this will start the host bus state machine prematurely. 3.3 dram interface in the following discussion the term row refers to the set of memory devices that are simultaneously selected by a ras# signal. a row may be composed of two or more single-sided simms, or one side (the same side) from two or more double-sided simms. an interleave is 72-bits wide (64 data bits plus 8 bits of ecc) and requires two 36 bit simms. the term page refers to the data within a row that is selected by a row address and is held active in the device waiting for a column address to be asserted. the mc interfaces the main memory dram to the host bus. for the 450kx, two basic dram configurations are supported2-way interleaved (or 2:1 interleaved), and non-interleaved (or 1:1 interleaved). in the 2-way and non-interleaved configurations, a row is made up of 4 simm sides and 2 simm sides respectively. there can be up to 1 gbyte of dram for a 2-way interleaved configuration and 512 mbytes of dram for a non-inter- leaved configuration as shown in table 22. the mc is fully configurable through the mcs configuration registers. configurations cannot be mixed. the mc does not support portions of the memory being 2-way interleaved and other portions being non-interleaved. the system does, however, support a 2-way interleaved design in which one interleave is populated (operates as a non-interleaved configuration). there is no restriction on which interleave is populated (0 or 1) to form a non-interleaved configuration, as long as all rows are populated in the same way. for the 450GX, three basic dram configurations are supported4-way interleaved (4:1 interleaved), 2-way interleaved, and non-interleaved. in the 4-way interleaved configuration, a row is made up of 8 36-bit simm sides. in the 2-way interleaved and non-interleaved configurations, a row is made up of 4 simm sides and 2 simm sides respectively. there can be up to 4 gbytes of dram for a 4-way interleaved configuration, 2gbytes for a 2-way interleaved configuration, and 1gbyte for a non-interleaved configuration.
126 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a table 22 provides a summary of the characteristics of memory configurations supported by the 450kx/gx mc. minimum values listed are obtained with single-sided simms, and maximum values are obtained with double- sided simms. refresh operation refresh for the memory array is handled automatically by the mc. the rate of refresh cycles is programmable in the memtim register (ac-afh). an alternative to a single refresh cycle is to stagger refreshes across the dram rows. refresh stagger allows the refresh power surge to be tailored to the system. this allows the system to select staggering of row refreshes by one clock increments for zero to seven cycles. while refreshing fewer rows at once increases the chance of a refresh request collision with a host request, it enables the system to handle the power surge caused by refresh. staggering refreshes within a group increases the time for the group refresh, but spreads the power demands over time, and thus allows larger groups to be refreshed. refresh staggering provides substantial power surge reduction over refreshing all rows simultaneously. table 22. minimum and maximum memory sizes for each configuration device non-interleaved 2-way interleaved 4-way interleaved min (inc) max min (inc) max min (inc) max 512k x 8 4 mb 16 mb 8 mb 32 mb 16 mb 128 mb 32 mb 64 mb 1m x 4 8 mb 32 mb 16 mb 64 mb 32 mb 256 mb 64 mb 128 mb 2m x 8 16 mb 64 mb 32 mb 128 mb 64 mb 512 mb 128 mb 256 mb 4m x 4 32 mb 128 mb 64 mb 256 mb 128 mb 1 gb 256 mb 512 mb 8m x 8 64 mb 256 mb 128 mb 512 mb 256 mb 2 gb 512 mb 1 gb 16m x 4 128 mb 512 mb 256 mb 1 gb 512 mb 4 gb 1 gb 2 gb the 450GX mc does not support portions of the memory being 4-way interleaved and other portions being non-interleaved or 2-way interleaved. the system does, however, support a 4-way or 2-way interleaved design in which one interleave is populated (operates as a non-interleaved configuration) or a 4-way interleaved design in which two interleaves are populated (operates as a 2-way configuration). there is no restriction on which interleaves are populated to form a non-interleaved or 2-way interleaved configuration, as long as all rows are populated in the same way. for the 450GX, two mcs can be used in a system permitting a maximum of 8 gbytes of main memory. when two controllers are present in a system, the memory configuration and operation of an mc is independent of the other mc. the omcnum signal determines the configuration address and the default base address of a controller. beyond this, the general behavior of each memory subsystem is identical.
preliminary 127 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 3.3.1 dram configurations the memory supported by the mc is arranged as 4 rows with 1 or 2 interleaves (8 rows with 1, 2, or 4 inter- leaves for the 450GX). this can be implemented with discrete memory devices, single-sided simms, or double- sided simms. systems in which adjacent rows of memory have a common cas# connection are a special case, and are selected via the cmd register (offset 4cC4fh). the primary example of this is a system constructed with double-sided simms having a common cas# connection between the two sides. for all the memory configuration types, the mc provides 4 logical ras# signals (8 for the 450GX); one per row. two copies of the ras# signals (rasax# and rasbx#) are provided for fanout. the mc provides 4 logical cas# signals (8 for the 450GX). two copies (casax# and casbx#) are provided for fanout. in the case of a common cas# connection between adjacent rows, there are only 2 logical cas# signals (one per pair of rows) for the 450kx and 4 logical cas# signals for the 450GX. in addition, the loading per cas# signal is doubled. to accommodate this, the mc combines the cas# signals for two rows (e.g. casa[1:0#] and casb[1:0]#) are driven with the same value and are used to drive the first two memory rows. the descriptions of the supported configurations that follow assume that the dram in the system is imple- mented with double-sided simms that do not have a common cas# connection and that do not have buffers on the simms. figure 2 shows the connections required for each double-sided simm (dssimm). note that these are simm connections and do not map one-to-one to mc signals. also shown is the symbol used to represent the 72-bit wide memory formed from two dssimms. figure 2. signal connections to a double-sided simm 3.3.1.1 memory interface component (mic) to interface with the data signals from the devices in the memory array, the mc utilizes a set of four memory interface components (mics), each 18 bits wide. these components multiplex data read from the interleaved memory, register data being written to memory, and provide the buffering required to drive the memory devices. all configurations utilize four of these devices. the interconnection of the mics and the memory devices is shown in figure 3. d[35:0] a[12:0] we# ras[x:x-1]# cas[x:x-1]# tw o d s s i m m s (word-wide e.g., 72 bits)
128 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a figure 3. mic to memory interconnections 3.3.1.2 4-way dram configuration (450GX only) mic mic mic mic i0d[17:0] i1d[17:0] i2d[17:0] i3d[17:0] i0d[35:18] i1d[35:18] i2d[35:18] i3d[35:18] i0d[53:36] i1d[53:36] i2d[53:36] i3d[53:36] i0d[71:54] i1d[71:54] i2d[71:54] i3d[71:54] mde[17:0] mde[35:18] mde[53:36] mde[71:54] miccmd[6:0]# i0d[71:0] = interleave 0 data bus. i1d[71:0] = interleave 1 data bus. i2d[71:0] = interleave 2 data bus. i3d[71:0] = interleave 3 data bus. mics in the 4-way interleaved dram configuration, the memory controller supports up to 8 rows of conventional dram. each of these rows can be up to 512 mbytes, using 64-mbit technology. this configuration is illustrated in figure 4, as implemented with dssimms. the basic structure of the 4-way interleaved memory (figure 4) is four 72-bit word wide connections from the dram time multiplexed to the mc. this multiplexing allows the mc to read or write memory at the rate of one 72-bit word each clock cycle and to hide much of the access latency of the dram devices. logically, the 4-way configuration requires eight ras# lines and eight cas# lines (one for each row). the ras# signals latch the row address in the four interleaves, and the cas# signals latch the column address in each interleave. ma[12:0] and we# are broadcast to all devices, and must be buffered to each dssimm. the exact buffer type used is system design dependent. the minimum memory size for this configuration is 4 mbytes using 4-mbit technology organized as 512kx8 devices (1 row, 4 mbytes, operating as non-interleaved). the maximum size is 4 gbytes using 64-mbit technology. mixing of row sizes is supported; however, within a row, all simms must be the same size.
preliminary 129 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) figure 4. 4-way interleaved configuration 3.3.1.3 2-way dram configuration in a 2-way interleaved dram configuration (figure 5), the memory controller supports up to 4 rows (8 rows for an 450GX) of 2-way interleaved dram. the minimum and maximum main memory sizes are listed in table 22.the mc supports mixing different row sizes; however, within a row, all simms must be the same size. ma[12:0] and we# are broadcast to all devices, and must be buffered to each dssimm. the exact buffer type used is system design dependent. ma[12:0], wex# cas[7:0]# ras[7:0]# dc dp to all memory devices mc m i c m i c m i c m i c a 2-way interleaved configuration may result from populating two interleaves of the 4:1 memory system shown in the previous section, or as a 2-way interleaved only system. the signal connections for 2-way interleaved memory are the same as those described for the 4-way interleaved configuration. there is no restriction on the connection of the two interleaves to the mic ports.
130 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a figure 5. 2-way interleaved configuration 3.3.1.4 non-interleaved dram configuration in this configuration, the mc supports up to 4 rows (8 rows for an 450GX) of non-interleaved dram. this configuration may result from populating any one interleave of a 2-way interleaved system (or 4-way inter- leaved system for the 450GX) described previously. note, however, that in practice, the non-interleaved config- uration is used only for minimum memory sizes. memory expansion usually occurs across interleaves before extending the number of rows. the mc supports mixing different row sizes. ma[12:0], wex# casx[3:0]# dc dp to all memory devices mc rasx[7:0]# rasx[3:0]# casx[7:0# m i c m i c m i c m i c
preliminary 131 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 3.4 clocks and reset 3.4.1 clocks the host bus clock is used for the mc and is input on the bclk pin. this clock is generated externally and distributed to host bus components by a low skew clock driver (figure 6). the clock driver provides multiple copies of the bus clock. the loading on the clock lines must be balanced to minimize clock skew among the components on the bus. . figure 6. clock distribution 3.4.2 reset when the system is initially powered up, the power supply must wait until all voltages are stable for at least one millisecond, and then assert the pwrgd signal. a transition from 0 to 1 on pwrgd resets the pci bridge (pb) and portions of the dc. the pb is responsible for resetting and configuring the dc and other host devices. during a hard reset, the mc initalizes its internal registers. when the dc receives a hard reset on reset#, it resets the dp and mic by asserting mirst#. mirst# on the dc should be connected to the mirst# on the dp and mic. when the pb (compatibility pb in an 450GX dual pb system) generates a hard reset, it also drives the appro- priate host data bus signals with the values specified in its configuration values driven on reset register. the mc captures the values it needs (see capture system configuration register description). y1 y2 y3 yn external low skew clock generator/driver bclk dc y4 y5 y6 ... host bus clock to pbs and other system bclk dp mic bclk bclks components
132 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 4.0 mc pinout and package information the pinout and package information for the 82453gx/kx, 82452gx/kx, and 82451gx/kx is shown in this section. pins unique to the 82450GX are shown in a list at the center of the figure. in the tables, the first name is the 450GX name. note that testlo pins must be pulled low with a 150 w resistor and testhi pins must be pulled to 3.3v with a 10k w resistor. gtlhi pins should be pulled up with 10k w to v tt . 4.1 82453kx/82453gx (dc) pin assignment figure 7. 82453kx/gx dc pin assignment (208-pin qfp) 208oridt.drw gnd gnd tck gnd tms tdi tdo trst# gnd gtlrefv gnd nc nc nc nc a35# a29# a30# a32# a33# a34# a22# a24# a27# a26# gnd vcc3 a31# a19# a21# a20# a23# a28# a16# a15# a18# a25# a12# a14# a11# a13# a17# a9# a7# a5# a8# a10# a6# a4# a3# gnd gnd pwrgd nc nc testhi sysden# syscmd4# syscmd3# syscmd2# syscmd1# syscmd0# memerr1# memerr0# gnd memcmd7# memcmd6# memcmd5# gnd dbsy# bnr# vcc3 gnd bclk reserved nc gnd trdy# berr# req2# aerr# req3# req0# req1# req4# rs2# rs0# rp# rsp# rs1# testlo testlo nc ads# hit# hitm# gnd ap0# breq0# ap1# binit# reset# gnd sbcerr# mirst# nc nc nc nc nc nc vcc3 gnd nc nc casa3# vcc3 gnd casb2# casa1# gnd casb0# casa0# nc nc nc nc nc nc gnd nc nc rasb3# rasa3# rasb2# rasa2# rasb1# gnd gnd 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 memcmd4# memcmd3# memcmd2# memcmd1# memcmd0# gnd gnd gnd gnd gnd casb3# casa2# casb1# vcc3 vcc3 vcc3 vcc3 mab9 gnd mab11 rasa1# rasb0# rasa0# we1# we0# mab12 maa12 maa11 mab10 maa10 maa9 mab8 maa8 mab7 gnd maa7 mab6 maa6 mab5 gnd maa5 maa4 mab3 maa3 mab2 maa2 mab1 gnd maa1 mab0 maa0 micmwc0# micmwc1# gnd miccmd0# miccmd1# miccmd2# nc mab4 miccmd3# miccmd4# miccmd5# miccmd6# vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 82453gx 55 57 118 119 120 121 122 123 126 127 140 141 142 143 144 145 148 149 omcnum0 syserr# casb7# casa7# casb6# casa6# casb5# casa5# casb4# casa4# rasb7# rasa7# rasb6# rasa6# rasb5# rasa5# rasb4# rasa4# 82453 dc qfp nc = reserved
preliminary 133 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) name pin# type a3# 50 i a4# 49 i a5# 45 i a6# 48 i a7# 44 i a8# 46 i a9# 43 i a10# 47 i a11# 40 i a12# 38 i a13# 41 i a14# 39 i a15# 35 i a16# 34 i a17# 42 i a18# 36 i a19# 29 i a20# 31 i a21# 30 i a22# 22 i a23# 32 i a24# 23 i a25# 37 i a26# 25 i a27# 24 i a28# 33 i a29# 17 i a30# 18 i a31# 28 i a32# 19 i a33# 20 i a34# 21 i a35# 16 i ads# 90 i aerr# 92 i/o ap0# 110 i ap1# 112 i bclk 80 i berr# 88 i/o binit# 113 i/o bnr# 77 i/o breq0# 111 o casa0# 139 o casa1# 135 o casa2# 133 o casa3# 129 o casa4#/nc 127 o casa5#/nc 123 o casa6#/nc 121 o casa7#/nc 119 o casb0# 138 o casb1# 134 o casb2# 132 o casb3# 128 o casb4#/nc 126 o casb5#/nc 122 o casb6#/nc 120 o casb7#/nc 118 o dbsy# 76 i/o gnd 1 v gnd 2 v gnd 4 v gnd 9 v gnd 11 v gnd 26 v gnd 51 v gnd 52 v gnd 66 v gnd 75 v gnd 79 v gnd 86 v gnd 91 v table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) (continued) name pin# type gnd 97 v gnd 100 v gnd 105 v gnd 106 v gnd 109 v gnd 115 v gnd 125 v gnd 131 v gnd 137 v gnd 147 v gnd 155 v gnd 156 v gnd 167 v gnd 177 v gnd 182 v gnd 193 v gnd 199 v gtlrefv 10 i hit# 107 i/o hitm# 108 i/o maa0 196 o maa1 194 o maa2 190 o maa3 188 o maa4 186 o maa5 184 o maa6 180 o maa7 178 o maa8 174 o maa9 172 o maa10 170 o maa11 168 o maa12 164 o mab0 195 o mab1 191 o mab2 189 o table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) (continued) name pin# type
134 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a mab3 187 o mab4 185 o mab5 181 o mab6 179 o mab7 175 o mab8 173 o mab9 171 o mab10 169 o mab11 165 o mab12 163 o memcmd0# 74 i/o memcmd1# 73 i/o memcmd2# 72 i/o memcmd3# 71 i/o memcmd4# 70 i/o memcmd5# 69 i/o memcmd6# 68 i/o memcmd7# 67 i/o memerr0# 65 i memerr1# 64 i mirst# 117 o miccmd0# 200 o miccmd1# 201 o miccmd2# 202 o miccmd3# 203 o miccmd4# 204 o miccmd5# 205 o miccmd6# 206 o micmwc0# 197 o micmwc1# 198 o omcnum/ 55 i testlo pwrgd 54 i rasa0# 160 o rasa1# 158 o rasa2# 153 o table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) (continued) name pin# type rasa3# 151 o rasa4#/nc 149 o rasa5#/nc 145 o rasa6#/nc 143 o rasa7#/nc 141 o rasb0# 159 o rasb1# 154 o rasb2# 152 o rasb3# 150 o rasb4#/nc 148 o rasb5#/nc 144 o rasb6#/nc 142 o rasb7#/nc 140 o req0# 94 i req1# 95 i req2# 89 i req3# 93 i req4# 96 i reserved 12 nc reserved 13 nc reserved 14 nc reserved 15 nc reserved 83 nc reserved 207 nc reset# 114 i rp# 102 i/o rs0# 101 i/o rs1# 99 i/o rs2# 98 i/o rsp# 103 i/o sbcerr# 116 o syscmd0# 63 o syscmd1# 62 o syscmd2# 61 o syscmd3# 60 o syscmd4# 59 o table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) (continued) name pin# type sysden# 58 o syserr#/ 57 i testhi tck 3 i tdi 6 i tdo 7 o testlo 56 i testlo 81 i testlo 82 i testlo 84 i testlo 85 i tms 5 i trdy# 87 i/o trst# 8 i vcc3 27 v vcc3 53 v vcc3 78 v vcc3 104 v vcc3 124 v vcc3 130 v vcc3 136 v vcc3 146 v vcc3 157 v vcc3 166 v vcc3 176 v vcc3 183 v vcc3 192 v vcc3 208 v we#0 162 o we#1 161 o table 23. 82453 kx/gx dc alphabetical pin list (208-pin qfp) (continued) name pin# type
preliminary 135 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 4.2 82452gx/82452kx (dp) pin assignment . figure 8. 82452 dp pin assignment (240-pin qfp) 240ori.drw gnd gnd tck testhi tms tdi tdo trst# d0# d2# gnd d1# d4# gnd d3# d6# gnd d5# d7# gnd vcc3 d8# d12# gnd d9# d14# gnd d10# d15# gnd d11# d13# gnd d16# d17# gnd d20# d18# d19# vcc3 gnd d21# gnd d22# d23# gnd d25# d24# gnd d26# d27# gnd d29# d30# gnd d28# d31# d32# gnd gnd gnd d35# d38# d33# gnd d34# d37# gnd gnd d44# d45# gnd d47# gnd d41# gnd d52# d49# gnd d48# d59# d57# gnd d54# d53# d50# gnd d56# d55# gnd d60# vcc3 d42# d51# d46# gnd d58# d62# gnd mdrdy0# mde0 mde1 mde2 mde3 mde4 mde5 mde6 mde7 vcc3 gnd gnd mde8 mde9 mde10 mde11 mde12 mde14 mde15 gnd mde16 mde19 mde20 mde21 mde22 gnd vcc3 mde23 mde24 mde25 mde26 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 53 54 55 56 57 58 59 60 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 d40# d43# gnd d36# d39# gnd gnd vcc3 d63# d61# mde13 mde17 mde18 vcc3 61 mde27 mde28 mde29 mde30 gnd mdrdy1# mde31 mde33 mde34 mde35 mde36 mde39 vcc3 gnd mde40 mde41 mde42 mde43 mde44 mde45 mde46 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 mde32 mde37 mde38 mde48 mde49 mde50 mde51 mde52 mde53 mde54 mde55 gnd gnd 170 171 172 173 174 175 176 177 178 179 180 gnd 169 mde47 gtlrefv mirst# gtlhi gtlhi gtlhi gnd gtlhi gtlhi drdy# gnd sysden# syscmd4# syscmd3# gnd syscmd1# memerr1# memerr0# memcmd7# memcmd6# memcmd3# memcmd2# memcmd1# memcmd0# gnd testlo gnd reserved mde71 mde70 testlo vcc3 syscmd2# syscmd0# memcmd5# mde67 mde66 mde65 mde64 gnd mde63 mde62 mde61 mde60 mde59 mde58 mde57 mde56 vcc3 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 gnd gtlhi gtlhi gnd gtlhi memcmd4# bclk vcc3 mde69 mde68 vcc3 240 reserved syserr# dep7# dep2# dep4# dep1# dep6# dep5# dep0# dep3# 216 227 229 230 232 233 235 236 237 82452gx 82452 dp qfp reserved = nc
136 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) signal pin# type bclk 204 i d0# 9 i/o d1# 12 i/o d2# 10 i/o d3# 15 i/o d4# 13 i/o d5# 18 i/o d6# 16 i/o d7# 19 i/o d8# 22 i/o d9# 25 i/o d10# 28 i/o d11# 31 i/o d12# 23 i/o d13# 32 i/o d14# 26 i/o d15# 29 i/o d16# 34 i/o d17# 35 i/o d18# 38 i/o d19# 39 i/o d20# 37 i/o d21# 42 i/o d22# 44 i/o d23# 45 i/o d24# 48 i/o d25# 47 i/o d26# 50 i/o d27# 51 i/o d28# 56 i/o d29# 53 i/o d30# 54 i/o d31# 57 i/o d32# 58 i/o d33# 65 i/o d34# 67 i/o d35# 63 i/o d36# 73 i/o d37# 68 i/o d38# 64 i/o d39# 74 i/o d40# 70 i/o d41# 83 i/o d42# 82 i/o d43# 71 i/o d44# 76 i/o d45# 77 i/o d46# 90 i/o d47# 79 i/o d48# 89 i/o d49# 87 i/o d50# 98 i/o d51# 84 i/o d52# 86 i/o d53# 96 i/o d54# 95 i/o d55# 103 i/o d56# 102 i/o d57# 93 i/o d58# 108 i/o d59# 92 i/o d60# 99 i/o d61# 106 i/o d62# 109 i/o d63# 105 i/o dep0#/ 236 i/o table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type gtlhi dep1#/ 232 i/o gtlhi dep2#/ 229 i/o gtlhi dep3#/ 237 i/o gtlhi dep4#/ 230 i/o gtlhi dep5#/ 235 i/o gtlhi dep6#/ 233 i/o gtlhi dep7#/ 227 i/o gtlhi drdy# 226 i/o gnd 1 v gnd 2 v gnd 11 v gnd 14 v gnd 17 v gnd 20 v gnd 24 v gnd 27 v gnd 30 v gnd 33 v gnd 36 v gnd 41 v gnd 43 v gnd 46 v gnd 49 v gnd 52 v gnd 55 v table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type
preliminary 137 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) gnd 59 v gnd 60 v gnd 62 v gnd 66 v gnd 69 v gnd 72 v gnd 75 v gnd 78 v gnd 80 v gnd 85 v gnd 88 v gnd 91 v gnd 94 v gnd 97 v gnd 101 v gnd 104 v gnd 107 v gnd 110 v gnd 121 v gnd 122 v gnd 131 v gnd 139 v gnd 149 v gnd 161 v gnd 170 v gnd 179 v gnd 180 v gnd 190 v gnd 200 v gnd 205 v gnd 221 v gnd 225 v gnd 228 v table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type gnd 231 v gnd 234 v gtlrefv 239 i mde0 112 i/o mde1 113 i/o mde2 114 i/o mde3 115 i/o mde4 116 i/o mde5 117 i/o mde6 118 i/o mde7 119 i/o mde8 123 i/o mde9 124 i/o mde10 125 i/o mde11 126 i/o mde12 127 i/o mde13 128 i/o mde14 129 i/o mde15 130 i/o mde16 132 i/o mde17 133 i/o mde18 134 i/o mde19 135 i/o mde20 136 i/o mde21 137 i/o mde22 138 i/o mde23 141 i/o mde24 142 i/o mde25 143 i/o mde26 144 i/o mde27 145 i/o mde28 146 i/o mde29 147 i/o table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type mde30 148 i/o mde31 151 i/o mde32 152 i/o mde33 153 i/o mde34 154 i/o mde35 155 i/o mde36 156 i/o mde37 157 i/o mde38 158 i/o mde39 159 i/o mde40 162 i/o mde41 163 i/o mde42 164 i/o mde43 165 i/o mde44 166 i/o mde45 167 i/o mde46 168 i/o mde47 169 i/o mde48 171 i/o mde49 172 i/o mde50 173 i/o mde51 174 i/o mde52 175 i/o mde53 176 i/o mde54 177 i/o mde55 178 i/o mde56 182 i/o mde57 183 i/o mde58 184 i/o mde59 185 i/o mde60 186 i/o mde61 187 i/o mde62 188 i/o table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type
138 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a mde63 189 i/o mde64 191 i/o mde65 192 i/o mde66 193 i/o mde67 194 i/o mde68 195 i/o mde69 196 i/o mde70 197 i/o mde71 198 i/o mdrdy0# 111 o mdrdy1# 150 o memcmd0# 206 i/o memcmd1# 207 i/o memcmd2# 208 i/o memcmd3# 209 i/o memcmd4# 210 i/o memcmd5# 211 i/o table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type memcmd6# 212 i/o memcmd7# 213 i/o memerr0# 214 o memerr1# 215 o mirst# 238 i reserved 199 syscmd#0 217 i syscmd#1 218 i syscmd#2 219 i syscmd#3 222 i syscmd#4 223 i sysden# 224 i syserr#/ 216 o reserved tck 3 i td0 7 o tdi 6 i table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type testhi 4 testlo 202 testlo 203 tms 5 i trst# 8 i vcc3 21 v vcc3 40 v vcc3 61 v vcc3 81 v vcc3 100 v vcc3 120 v vcc3 140 v vcc3 160 v vcc3 181 v vcc3 201 v vcc3 220 v vcc3 240 v table 24. 82452 kx/gx dp alphabetical pin list (240-pin qfp) (continued) signal pin# type
preliminary 139 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) figure 9. 82452 dp pin assignment (256 bga) 256bgapn.drw trst# tms tdi nc mde45 mde48 mde51 mde52 d1# d2# td0 vcc3 mde42 mde44 mde47 vcc3 d3# gnd d4# d0# mde40 mde41 mde42 mde46 d7# d5# d6# gnd mde37 mde38 mde39 gnd gnd gnd gnd gnd gnd gnd gnd d12# d8# nc gnd gnd gnd gnd gnd gnd mde36 mde35 mde34 mde33 gnd gnd gnd gnd gnd gnd mde30 mdrdy1# mde31 mde32 d10# d9# d14# vcc3 gnd gnd gnd gnd gnd gnd d15# d11# d13# gnd vcc3 mde28 mde27 mde29 gnd gnd gnd gnd gnd gnd d16# d17# d20# d18# mde23 mde24 mde25 mde26 d22# d23# d24# d27# mde14 mde17 mde18 mde19 d25# gnd d29# vcc3 vcc3 mde12 mde15 mde16 d26# d30# gnd nc mde9 mde10 nc mde13 d28# d32# nc gnd nc vcc3 d34# gnd gnd vcc3 d59# gnd gnd mdrdy0# vcc3 mde5 gnd nc nc mde11 d31# nc nc nc d35# gnd d43# d39# d47# d51# d46# d53# d56# gnd mde0 mde4 nc nc nc mde8 nc nc nc nc d38# d37# gnd d44# nc d41# d48# d54# d60# d63# d58# mde1 mde3 mde7 nc nc nc nc nc nc d33# d40# d36# d45# d42# d52# d49# d57# d50# d55# d61# d62# mde2 mde6 nc nc gnd gnd gnd gnd gnd gnd d19# d21# gnd gnd gnd mde20 mde21 mde22 a b c d e f g h l m n p r t u v j k y w a b c d e f g h l m n p r t u v j k y w 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd nc drdy# sys- cmd4# sys- cmd2# reserved mem- cmd6# mem- cmd2# mem- cmd1# testlo mde71 mde68 mde65 mde61 mde60 mde57 nc nc gtlhi gtlhi gtlhi gtlhi gtlhi gtlhi gtlhi gtlhi mem- cmd3# nc nc nc nc nc gtlrefv gnd sys- cmd3# sys- cmd0# mem- cmd7# bclk testlo mde70 mde67 mde64 mde62 nc testhi nc mirst# gnd sysden# sys- cmd1# mem- err0# mem- cmd4# mem- cmd0# mde69 mde66 mde59 mde56 mde54 mde53 gnd nc nc nc nc tck gnd gnd mem- err1# vcc3 vcc3 vcc3 gnd gnd mem- cmd5# reserved mde63 mde58 mde55 mde50 mde49 82452gx a4 a3 a8 b3 b4 b5 c6 d5 d7 dep1# dep0# syserr# dep3# dep6# dep4# dep2# dep5# dep7# 82452 dp, bga nc = reserved
140 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a table 25. 82452kx/gx dp alphabetical pin list (256 bga) signal ball# type bclk b11 i d0# g4 i/o d1# f1 i/o d2# f2 i/o d3# g1 i/o d4# g3 i/o d5# h2 i/o d6# h3 i/o d7# h1 i/o d8# j3 i/o d9# k2 i/o d10# k1 i/o d11# l2 i/o d12# j2 i/o d13# l3 i/o d14# k3 i/o d15# l1 i/o d16# m1 i/o d17# m2 i/o d18# m4 i/o d19# n1 i/o d20# m3 i/o d21# n2 i/o d22# p1 i/o d23# p2 i/o d24# p3 i/o d25# r1 i/o d26# t1 i/o d27# p4 i/o d28# u1 i/o d29# r3 i/o d30# t2 i/o d31# v1 i/o d32# u2 i/o d33# y5 i/o d34# u7 i/o d35# v5 i/o d36# y7 i/o d37# w6 i/o d38# w5 i/o d39# v8 i/o d40# y6 i/o d41# w10 i/o d42# y9 i/o d43# v7 i/o d44# w8 i/o d45# y8 i/o d46# v11 i/o d47# v9 i/o d48# w11 i/o d49# y11 i/o d50# y13 i/o d51# v10 i/o d52# y10 i/o d53# v12 i/o d54# w12 i/o d55# y14 i/o d56# v13 i/o d57# y12 i/o d58# w15 i/o d59# u11 i/o d60# w13 i/o d61# y15 i/o d62# y16 i/o d63# w14 i/o drdy# a5 i/o table 25. 82452kx/gx dp alphabetical pin list (256 bga) (continued) signal ball# type dep0#/ a3 i/o gtlhi dep1#/ a4 i/o gtlhi dep2#/ c6 i/o gtlhi dep3#/ b3 i/o gtlhi dep4#/ b5 i/o gtlhi dep5#/ d5 i/o gtlhi dep6#/ b4 i/o gtlhi dep7#/ d7 i/o gtlhi gtlrefv b2 i mdrdy0# u14 o mdrdy1# k19 o mde0 v15 i/o mde1 w16 i/o mde2 y17 i/o mde3 w17 i/o mde4 v16 i/o mde5 u16 i/o mde6 y18 i/o mde7 w18 i/o mde8 v20 i/o mde9 t17 i/o mde10 t18 i/o mde11 u20 i/o mde12 r18 i/o mde13 t20 i/o table 25. 82452kx/gx dp alphabetical pin list (256 bga) (continued) signal ball# type
preliminary 141 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) mde14 p17 i/o mde15 r19 i/o mde16 r20 i/o mde17 p18 i/o mde18 p19 i/o mde19 p20 i/o mde20 n18 i/o mde21 n19 i/o mde22 n20 i/o mde23 m17 i/o mde24 m18 i/o mde25 m19 i/o mde26 m20 i/o mde27 l19 i/o mde28 l18 i/o mde29 l20 i/o mde30 k20 i/o mde31 k18 i/o mde32 k17 i/o mde33 j20 i/o mde34 j19 i/o mde35 j18 i/o mde36 j17 i/o mde37 h20 i/o mde38 h19 i/o mde39 h18 i/o mde40 g20 i/o mde41 g19 i/o mde42 f20 i/o mde43 g18 i/o mde44 f19 i/o mde45 e20 i/o mde46 g17 i/o table 25. 82452kx/gx dp alphabetical pin list (256 bga) (continued) signal ball# type mde47 f18 i/o mde48 e19 i/o mde49 d20 i/o mde50 d19 i/o mde51 e18 i/o mde52 e17 i/o mde53 c20 i/o mde54 c19 i/o mde55 d18 i/o mde56 c17 i/o mde57 a18 i/o mde58 d16 i/o mde59 c16 i/o mde60 a17 i/o mde61 a16 i/o mde62 b16 i/o mde63 d14 i/o mde64 b15 i/o mde65 a15 i/o mde66 c14 i/o mde67 b14 i/o mde68 a14 i/o mde69 c13 i/o mde70 b13 i/o mde71 a13 i/o memcmd0# c11 i/o memcmd1# a11 i/o memcmd2# a10 i/o memcmd3# b10 i/o memcmd4# c10 i/o memcmd5# d10 i/o memcmd6# a9 i/o memcmd7# b9 i/o table 25. 82452kx/gx dp alphabetical pin list (256 bga) (continued) signal ball# type memerr0# c9 o memerr1# d9 o mirst# c4 i reserved d12 sysden# c7 i syscmd0# b8 i syscmd1# c8 i syscmd2# a7 i syscmd3# b7 i syscmd4# a6 i syserr#/ a8 o reserved tck d1 i td0 f3 o tdi e3 i testhi c1 i testlo a12 i testlo b12 i tms e2 i trst# e1 i table 25. 82452kx/gx dp alphabetical pin list (256 bga) (continued) signal ball# type
142 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 4.3 82451kx/82451gx (mic) pin assignment . figure 10. 82451kx/gx mic pin assignment (144-pin qfp) 1. ground pins within the brackets are thermal connections. table 26. 82452kx/gx dp vcc, ground, and no connect pins (256 bga) signal bga ball# vcc3 f4, k4, r4, u6, u10, u15, r17, l17, f17, d6, d11, d15 gnd a1, d4, d8, d13, d17, h4, n4, u4, u8, u13, u17, h17, n17, g2, j1, l4, n3, r2, t3, v6, w7, u9, u12, v14, c15, b6, c5, [h8, h9, h10, h11, h12, h13, j8, j9, j10, j11, j12, j13, k8, k9, k10, k11, k12, k13, l8, l9, l10, l11, l12, l13, m8, m9, m10, m11, m12, m13, n8, n9, n10, n11, n12, n13](1) nc b1, c2, d2, d3, e4, j4, t4, u3, v2, w1, v3, w2, y1, w3, y2, w4, v4, u5, y3, y4, w9, v17, y19, v18, w19, y20, t19, w20, v19, u19, u18, b20, c18, b19, a20, c3, a2, c12, a19, b17, b18 144oridt.drw vcc3 reset# miccmd6# miccmd5# miccmd4# miccmd3# miccmd2# miccmd1# miccmd0# micmwc# mdrdy# mde17 mde16 mde15 mde14 mde13 mde12 mde11 mde10 gnd vcc3 mde9 mde8 mde7 mde6 mde5 mde4 mde3 mde2 gnd testlo mde1 mde0 testlo testlo vcc3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 104 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 gnd gnd tck trst# nc tdo iod0 tdi gnd tms iod1 iod2 iod3 iod4 iod5 iod6 gnd iod7 iod8 iod10 gnd vcc3 iod11 iod14 iod15 gnd iod16 iod17 i1d0 i1d1 i1d2 gnd gnd iod9 iod12 iod13 gnd gnd bclk gnd testlo testlo nc nc nc nc nc nc vcc3 gnd nc nc nc nc nc nc gnd nc nc nc nc nc nc vcc3 gnd nc nc nc nc nc gnd gnd i1d3 vcc3 i1d5 i1d4 i1d6 nc nc nc nc nc gnd nc nc nc vcc3 gnd nc i1d15 i1d14 i1d13 gnd i1d12 i1d10 i1d7 vcc3 gnd i1d9 nc nc nc i1d17 vcc3 nc i1d16 i1d11 i1d8 82451gx 43 44 45 46 47 48 51 52 53 54 55 56 58 59 60 61 62 63 66 67 68 69 70 74 75 76 77 78 79 81 82 83 84 85 86 89 i3d17 i3d16 i3d15 i3d14 i3d13 i3d12 i3d11 i3d10 i3d9 i3d8 i3d7 i3d6 i3d5 i3d4 i3d3 i3d2 i3d1 i3d0 i2d17 i2d16 i2d15 i2d14 i2d13 i2d12 i2d11 i2d10 i2d9 i2d8 i2d7 i2d6 i2d5 i2d4 i2d3 i2d2 i2d1 i2d0 82451 mic qfp nc = reserved
preliminary 143 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) table 27. 82451 kx/gx mic alphabetical pin list (144-pin qfp) signal pin# type bclk 39 i gnd 20 v gnd 30 v gnd 37 v gnd 38 v gnd 40 v gnd 50 v gnd 57 v gnd 65 v gnd 71 v gnd 72 v gnd 80 v gnd 88 v gnd 95 v gnd 103 v gnd 109 v gnd 110 v gnd 116 v gnd 123 v gnd 128 v gnd 136 v gnd 143 v gnd 144 v i0d0 138 i/o i0d1 134 i/o i0d2 133 i/o i0d3 132 i/o i0d4 131 i/o i0d5 130 i/o i0d6 129 i/o i0d7 127 i/o i0d8 126 i/o i0d9 125 i/o i0d10 124 i/o i0d11 121 i/o i0d12 120 i/o i0d13 119 i/o i0d14 118 i/o i0d15 117 i/o i0d16 115 i/o i0d17 114 i/o i1d0 113 i/o i1d1 112 i/o i1d2 111 i/o i1d3 107 i/o i1d4 106 i/o i1d5 105 i/o i1d6 104 i/o i1d7 101 i/o i1d8 100 i/o i1d9 99 i/o i1d10 98 i/o i1d11 97 i/o i1d12 96 i/o i1d13 94 i/o i1d14 93 i/o i1d15 92 i/o i1d16 91 i/o i1d17 90 i/o i2d0/nc 89 i/o i2d1/nc 86 i/o i2d2/nc 85 i/o i2d3/nc 84 i/o i2d4/nc 83 i/o i2d5/nc 82 i/o i2d6/nc 81 i/o table 27. 82451 kx/gx mic alphabetical pin list (144-pin qfp) (continued) signal pin# type i2d7/nc 79 i/o i2d8/nc 78 i/o i2d9/nc 77 i/o i2d10/nc 76 i/o i2d11/nc 75 i/o i2d12/nc 74 i/o i2d13/nc 70 i/o i2d14/nc 69 i/o i2d15/nc 68 i/o i2d16/nc 67 i/o i2d17/nc 66 i/o i3d0/nc 63 i/o i3d1/nc 62 i/o i3d2/nc 61 i/o i3d3/nc 60 i/o i3d4/nc 59 i/o i3d5/nc 58 i/o i3d6/nc 56 i/o i3d7/nc 55 i/o i3d8/nc 54 i/o i3d9/nc 53 i/o i3d10/nc 52 i/o i3d11/nc 51 i/o i3d12/nc 48 i/o i3d13/nc 47 i/o i3d14/nc 46 i/o i3d15/nc 45 i/o i3d16/nc 44 i/o i3d17/nc 43 i/o mde0 33 i/o mde1 32 i/o mde2 29 i/o mde3 28 i/o table 27. 82451 kx/gx mic alphabetical pin list (144-pin qfp) (continued) signal pin# type
144 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a mde4 27 i/o mde5 26 i/o mde6 25 i/o mde7 24 i/o mde8 23 i/o mde9 22 i/o mde10 19 i/o mde11 18 i/o mde12 17 i/o mde13 16 i/o mde14 15 i/o mde15 14 i/o mde16 13 i/o mde17 12 i/o mdrdy# 11 i miccmd0# 9 i miccmd1# 8 i miccmd2# 7 i miccmd3# 6 i miccmd4# 5 i miccmd5# 4 i miccmd6# 3 i micmwc# 10 i mirst# 2 i reserved 140 nc tck 142 i tdi 137 i tdo 139 o testlo 31 i testlo 34 i testlo 35 i testlo 41 i testlo 42 i table 27. 82451 kx/gx mic alphabetical pin list (144-pin qfp) (continued) signal pin# type tms 135 i trst# 141 i vcc3 1 v vcc3 21 v vcc3 36 v vcc3 49 v vcc3 64 v vcc3 73 v vcc3 87 v vcc3 102 v vcc3 108 v vcc3 122 v table 27. 82451 kx/gx mic alphabetical pin list (144-pin qfp) (continued) signal pin# type
preliminary 145 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) 4.4 82453kx/82453gx (dc) package dimensions . figure 11. dc package physical dimensions (208-pin qfp) table 28. dc package physical dimensions (208-pin qfp) dim millimeters inches dim millimeters inches a 30.6 0.4 1.205 0.016 j 0.5 (t.p.) 0.020 (t.p.) b 28.0 0.2 1.102 0.008 k 1.3 0.2 0.051 0.008 c 28.0 0.2 1.102 0.008 l 0.5 0.2 0.020 0.008 d 30.6 0.4 1.205 0.016 m 0.15 0.05 0.006 0.002 f 1.25 0.49 n 0.075 0.003 g 1.25 0.049 p 3.7 0.0126 h 0.20 0.05 0.008 0.002 q 0.4 0.1 0.016 0.004 i 0.08 0.003 s 3.8 max 0.150 max 240pin.drw a b 180 181 240 1 f g d c 60 61 121 120 j h m i n p k l m enlarged detail of lead end q s 2 o - 2 + 4 o o top
146 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 4.5 82452kx/82452gx (dp) package dimensions . figure 12. dp package physical dimensions (240-pin qfp ) table 29. dp physical package dimensions (240-pin qfp ) dim millimeters inches dim millimeters inches a 34.6 0.3 1.362 0.012 j 0.5 (t.p.) 0.020 (t.p.) b 32.0 0.2 1.260 0.008 k 1.3 0.2 0.051 0.008 c 32.0 0.2 1.260 0.008 l 0.5 0.2 0.020 0.008 d 34.6 0.3 1.362 0.012 m 0.15 0.05 0.006 0.002 f 1.25 0.049 n 0.1 0.004 g 1.25 0.049 p 3.2 0.126 h 0.22 0.08 0.009 0.003 q 0.4 0.1 0.016 0.004 i 0.08 0.003 s 3.8 max 0.150 max 240pin.drw a b 180 181 240 1 f g d c 60 61 121 120 j h m i n p k l m enlarged detail of lead end q s 2 o - 2 + 4 o o top
preliminary 147 a 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) figure 13. dp package dimensions (256 bga) top view 27.00 24.00 16.10 27.00 24.00 16.10 1.00 dia. 45 chamfer 4 places mold compound printed wiring board 1.27 1.27 1.435 1.435 printed wiring board 256 x 0.76 solder balls bottom view pin one corner a b c d e f g h l m n p r t u v j k y w 2019181716151413121110 9 8 7 6 5 4 3 2 1 1.27 27.00 24.00 1.53 side view 27.00 24.00 0.36 0.60 1.17 2.13 mold compound printed wiring board end view 256bgaor.drw 15 typ. all sides 15 typ. all sides 1.435 1.27 typ. solder ball pin one corner o o
148 preliminary 82453kx/gx, 82452kx/gx, 82451kx/gx (mc) a 4.6 82451kx/82451gx (mic) package dimensions . figure 14. mic package physical dimensions (144-pin qfp) table 30. mic package physical dimensions (144-pin qfp) dim millimeters inches dim millimeters inches a 22.0 0.4 0.866 0.016 j 0.5 (t.p.) 0.020 (t.p.) b 20.0 0.2 0.787 0.008 k 1.0 0.2 0.039 0.008 c 20.0 0.2 0.787 0.008 l 0.5 0.2 0.020 0.008 d 22.0 0.4 0.866 0.016 m 0.15 0.05 0.006 0.002 f 1.25 0.049 n 0.10 0.004 g 1.25 0.049 p 2.7 0.106 h 0.20 0.05 .008 q 0.1 0.1 0.004 0.004 i 0.08 0.003 s 3.0 max 0.119 max 144pin.drw a b 108 109 144 1 f g d c 36 37 73 72 j h n p k enlarged detail of lead end q s l m i 5 5 +/- o m o top
preliminary 149 a pciset electrical specifications chapter 4 pciset electrical specifications
150 preliminary pciset electrical specifications a
preliminary 151 a pciset electrical specifications 1.0 electrical characteristics this section contains the electrical characteristics associated with the intel 450kx/gx pcisets. this includes information on power consumption, ac and dc signal timing information for gtl+ and non-gtl+ signals. to ensure functionality and reliability, the intel 450kx/gx pcisets are specified for proper operation when t c (case temperature) is within the specified range of 0c to 85c. for more information on measuring t c in your system, please refer to the pentium pro family developers manual: specifications . most of the pentium pro processor signals use a variation of the low voltage gtl (gunning transceiver logic). for more information on this technology refer to the pentium pro family developers manual: specifications . 1.1 test pins and unused pins for reliable operation, always connect unused inputs to an appropriate signal level. unused gtl+ inputs should be pulled-up to v tt with a 25 w to 10k w resistor. unused active low 3.3v inputs should be pulled-up to 3.3v with a 10k w resistor. unused active high inputs should be pulled to ground (vss) with a 1k w resistor. when connecting bidirectional signals to power or ground, a resistor must be used. when tying any signal to power or ground, a resistor will also allow for fully testing the processor and pciset after board assembly. it is suggested that ~10k w resistors be used for pull-ups and ~1k w resistors be used as pull-downs. in the 450kx/gx qfp and bga pinlists, in section 3.0 of chapter 2 and chapter 3, all signals labeled ?testlo? should be pulled to gnd with a 1k w resistor. signals labeled ?testhi? should be pulled up to v cc 3 with a 10k w resistor. signals labeled ?gtlhi? should be pulled up to v tt with a 10k w resistor. all reserved and nc pins must remain unconnected. 1.2 signal groups in order to simplify the following discussion, signals have been combined into groups of like characteristics in table 1. see section 3.0 in chapter 2 and chapter 3 for a description of the signals and their functions. all pins of the intel 450GX pciset are listed here. not all of these signals are available on the intel 450kx pciset. the following pins do not exist on the intel 450kx pciset: casa[7:4]#, casb[7:4]#, dep#[7:0], i2d[17:0], i3d[17:0], iognt#, ioreq#, omcnum, rasa[7:4]#, rasb[7:4]#, syserr# . table 1. signal groups pin group signals notes gtl+ input a[35:3]# , ads# , ap[1:0]# , req[4:0]# , rp# , reset# (1) gtl+ output breq0# gtl+ i/o a[35:3]# , ads# , aerr#, ap[1:0]# , berr#, binit#, bnr#, bpri#, d[63:0]#, dbsy#, defer#, dep[7:0]#, drdy#, hit#, hitm#, lock#, req[4:0]# , reset#, rp# , rs[2:0]#, rsp#, trdy# (1) cmos input, 5v tolerant iognt#, flshbf#, memreq#, pclkin, pgnt#, recven cmos input, 3.3v bclk, mdrdy[1:0]#, memcmd[7:0]#, memerr[1:0]#, mirst# , omcnum, pwrgd, syscmd[4:0]#, sysden#, tck, tdi, tms, trst# cmos output, 6ma, 5v tolerant flush#, init#, pcirst#, smiact# cmos output, 6ma, 3.3v memerr[1:0]#, syscmd[4:0]#, syserr#, tdo
152 preliminary pciset electrical specifications a 1.2.1 the power good signal pwrgd pwrgd is a 3.3v input to the pci bridge and memory controller components. it is expected that this signal is a clean indication that the clocks and the 3.3v, vcc pci supplies are within their specifications. clean implies that pwrgd will remain low, (capable of sinking leakage current) without glitches, from the time that the power supplies are turned on until they become valid. the signal will then transition monotonically to a high (3.3v) state with the transition not taking longer than 100ns. pwrgd needs to be negated for at least 10 bclks before this transition from low to high can take place. figure 1 illustrates the relationship of pwrgd to bclk and the system reset signals. the pwrgd inputs to the intel 450kx/gx pcisets and to the pentium pro processor(s) should be driven with an and of power-good signals from the 5v, 3.3v and vccp supplies. the output of this logic should be a 3.3v level and should have a pull-down resistor at the output to cover the period when this logic is not receiving power. 1. italicized signals are inputs on one device and i/o on another device: a[35:3]#, ads#, ap[1:0]#, req[4:0]#, rp#, and reset# are inputs to the dc, and i/o on the pb. mirst# is an output from the dc and an input to the dp and mics. 2. sbcerr# is an open-drain signal. 3. pci signals are both 3.3v and 5v tolerant. the drive and receive strength for the pci signals is set by the vcc pci input (pcibus voltage). for additional details, see the pci local bus specification, rev 2.0. cmos output, 12ma, 5v tolerant creset#, memack#, preq# cmos output, 12ma, 3.3v casa[7:0]#, casb[7:0]#, ma0[12:0], ma1[12:0], micmwc[1:0]#, rasa[7:0]#, rasb[7:0]#, reset#, sbcerr#, sysden#, we[1:0]# (2) cmos output, 18ma, 3.3v mdrdy[1:0]#, miccmd[6:0]#, mirst# cmos i/o, 6ma, 5v tolerant pclk cmos i/o, 6ma, 3.3v memcmd[7:0]# cmos i/o, 12ma, 5v tolerant i0d[17:0], i1d[17:0], i2d[17:0], i3d[17:0] cmos i/o, 12ma, 3.3v ioreq#, mde[71:0] pci signals, 24ma ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, plock#, ptrdy#, serr#, stop# (3) power gnd, gtlvref, vcc 3 , vcc pci table 1. signal groups (continued) pin group signals notes
preliminary 153 a pciset electrical specifications figure 1. pwrgd relationship 1.3 maximum ratings table 2 contains stress ratings for the intel 450kx/gx pcisets. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. the pcisets should not receive a clock while subjected to these conditions. functional operating conditions are given in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the intel 450kx/gx pcisets contain protective circuitry to resist damage from static discharge, one should always take precautions to avoid high static voltages or electric fields . 1. parameter applies to gtl+ signal group only 2. parameter applies to 3.3v and jtag signal groups only 3. parameter applies to 5v tolerant signal groups and pci signals only. v cc-pci is the voltage level of the pci bus. table 2. absolute maximum ratings sym parameter min max unit notes v cc 3 3.3v supply voltage with respect to vss -0.5 4.3 v v in gtl+ buffer dc input voltage with respect to vss -0.5 v cc 3 + 0.5 (not to exceed 4.3) v(1) v in 3 3.3v dc input voltage with respect to vss -0.5 v cc 3 + 0.9 (not to exceed 4.7) v(2) v in 5 5v tolerant dc input voltage with respect to vss -0.5 v cc-pci + 0.5 v (3) t stor storage temperature -65 150 c 3.3v vcc_pci bclk pwrgd min inactive pulse width = 10 bclks reset# mi_rst# creset#
154 preliminary pciset electrical specifications a 1.4 dc specifications the following tables list the dc specifications associated with the intel 450kx/gx pcisets. care should be taken to read any notes associated with each parameter listed. table 5 lists the specification for the gtl+ termination voltage (v tt ) and the gtl+ reference voltage (v ref ). 1. includes power dissipated in the gtl+ buffers. 2. i ss is the maximum supply current consumption when all gtl+ signals are low. it is the sum of icc3 and gtl+ current. table 3. voltage and temperature specifications sym parameter min typ max unit notes v cc 3 device vcc 3.13 3.3 3.46 v 5% v cc-pci (3.3) pci vcc for 3.3 v pci operation 3.0 3.3 3.6 v 10% v cc-pci (5) pci vcc for 5.0 v pci operation 4.5 5.0 5.5 v 10% i cc-pci clamping diode leakage current 2 ma at 33mhz t c operating case temperature 0 85 c table 4. power specifications sym parameter max unit notes p max pb max power dissipation 2.4 w (1) p max dc max power dissipation 1.13 w (1) p max dp max power dissipation 2.3 w (1) p max mic max power dissipation 0.69 w i cc 3 pb max power supply current 640 ma i cc 3 dc max power supply current 370 ma symbol parameter max unit notes i cc 3 dp max power supply current 460 ma i cc 3 mic max power supply current 200 ma i ss pb max v ss current 4800 ma (2) i ss dc max v ss current 600 ma (2) i ss dp max v ss current 4400 ma (2) i ss mic max v ss current 200 ma table 5. gtl+ bus dc specifications sym parameter min typ max unit notes v tt bus termination voltage 1.35 1.5 1.65 v 10% v ref input reference voltage 2/3 v tt - 2% 2/3 v tt 2/3 v tt +2% v 2%
preliminary 155 a pciset electrical specifications some of the signals on the pb, dc, and dp are in the gtl+ signal group. these signals are specified to be terminated to 1.5v. the dc specifications for these signals are listed in table 6. the dc specifications for the non-gtl+ signal groups are listed in table 7. a specification covers 3.3v and 5v tolerant buffers, unless otherwise stated. 1. refer to the 450kx and 450GX ringback specification for additional information regarding noise limits. 2. parameter measured into a 25 w resistor to v tt (1.5v). 3. the output high voltage level is determined by v tt. 4. (0 v in v tt ) 5. (0 v out v tt ) 6. total of buffer and package parasitics. table 6. dc specifications (gtl+ signal groups) sym parameter min max unit notes v il input low voltage -0.3 v ref - 0.1 v (1) v ih input high voltage v ref + 0.1 1.8 v (1) v ol output low voltage 0.30 0.55 v (2) v oh output high voltage -- -- v (3) i ol output low current 38 48 ma (2) i li input leakage current + 15 m a(4) i ref reference voltage current + 15 m a i lo output leakage current + 15 m a(5) c pin capacitance 10 pf (6)
156 preliminary pciset electrical specifications a 1. the interleave databus signals (ixdxx) can interface to 3v or 5v dram. these signals are 5v tolerant. 2. (0 v in v cc 3 ) -100 m a for pins with 50k w pullups, +100 m a for pins with 50k w pulldowns. pins with 50k w internal pullups: miccmd#, micmwc#, mdrdy#, reset, memcmd#, syscmd#, memerr#, syserr# pins with 50k w internal pulldowns: mde[71:0]#, ixd[17:0] 3. (0 v out v cc 3 ) 4. except bclk, tck table 7. dc specifications (non-gtl+ groups) sym pin group parameter min max unit notes v il cmos input input low voltage 0.8 v v il-pci pci input low voltage - 0.5 0.8 v v ih 3.3v cmos input input high voltage 2.0 3.6 v (1) v ih-5v 5v tolerant input input high voltage 2.0 5.0 v v ih-pci pci input high voltage 2.0 v cc-pci +0.5 v v ol cmos 6, 12, 18ma output low voltage 0.40 v at 4ma v ol-pci pci output low voltage 0.55 v v oh cmos 6, 12, 18ma output high voltage v cc 3-0.1 v v oh-pci pci output high voltage 2.4 v i ol-6 cmos 6ma output low current 6.0 ma at v ol = 0.4v i ol-12 cmos 12ma output low current 12.0 ma at v ol = 0.4v i ol-18 cmos 18ma output low current 18.0 ma at v ol = 0.4v i ol-pci pci output low current 6.0 ma i il cmos input input leakage current 100 m a(2) i lo cmos 6, 12, 18ma output leakage current 10 m a(3) i il-pci pci input leakage current 70 m a i ol-pci pci output leakage current 10 m a c in all input capacitance 10 pf (4) c o all output capacitance 10 pf c i/o all i/o capacitance 10 pf c bclk bclk bclk capacitance 8 pf c tck tck tck capacitance 8 pf
preliminary 157 a pciset electrical specifications 1.5 ac specifications the following tables list the ac specifications associated with the intel 450GX pcisets. care should be taken to read any notes associated with each parameter listed. table 10, contains ac specifications for the cmos signals. please note that the pci signals are specified with reference to the pclkin; the testability signals are specified with reference to the tck, and all other signals reference the system bus clock, bclk 1. measured at rising edge of bclk crossing 1.5v. 2. please refer to the pci specification 2.0 for more details. 1. values correspond to input waveforms as specified in the gtl+ interface specification in pentium pro processor developers manual: specifications . a waveform with less than 200mv of overdrive is acceptable if it meets the criteria in figure 5. how- ever, in this case, the minimum setup specification will be impacted by 1ns, making setup min 5.5ns. an example of a signal that would benefit from this derating is shown in figure 6. 2. outputs measured into 25 w tied to 1.5v. measurement made at 1.0v crossing. table 8. ac specifications (clock signal groups) symbol parameter min max unit figure notes f bclk frequency 50.00 66.67 mhz t1 bclk period 15 20 ns 2.2 t2 bclk period stability 300 ps (1) t3 bclk high time 6 ns 2.2 at > 2.0v t4 bclk low time 6 ns 2.2 at < 0.8v t5 bclk rise time 0.3 1.5 ns 2.2 0.8-2.0v t6 bclk fall time 0.3 1.5 ns 2.2 2.0-0.8v t7 pclkin period 30 ns (2) t44 tck rise/fall time 0 50 ns t44a tck frequency 16 mhz table 9. ac specifications (gtl+ signals) symbol parameter setup min hold min delay min delay max unit notes t8 gtl+ inputs 4.5 0.3 ns (1) t9 gtl+ outputs 1.0 6.0 ns (2) t10 gtl+ i/o 4.5 0.3 1.0 6.0 ns (1) (2)
158 preliminary pciset electrical specifications a . table 10. ac specifications (cmos signals) sym parameter setup min hold min delay min delay max unit notes pci side signals t11 ad[31:0], c/be[3:0]#, ptrdy#, stop#, plock#, devsel#, par, irdy#, frame#, perr#, serr# 7.0 0.0 2.0 11.0 ns (1) t11a preq# 2.0 12.0 ns (1) t12 pgnt# 10.0 0.0 ns (1) compatibility bridge signals t13 flshbf#, memreq# 12.0 0.0 ns t14 memack# 2.0 12.0 ns (2) bridge to bridge signals t15 i/oreq# 3.0 0.6 2.0 7.0 ns (3) t16 i/ognt# 3.0 0.6 ns (3) memory interface signalsdp t17a mde[71:0] ? write cycle 2.0 0.9 1.2 7.1 ns (3) t18 mdrdy[1:0]# 1.2 5.9 ns (3) t19 memcmd[7:0]# 1.9 0.8 1.4 5.9 ns (3) memory interface signalsdc t20 micmwc[0:1]# 1.1 5.3 ns (3) t21 miccmd[6:0]# 1.0 5.0 ns (3) t22 casa[7:0]#, casb[7:0]# 1.1 5.3 ns (3) (4) t23 rasa[7:0]#, rasb[7:0]# 1.1 5.3 ns (3) (4) t24 ma0[12:0], ma1[12:0] 1.1 5.3 ns (3) t25 we0#, we1# 1.1 5.3 ns (3) t26 memcmd[7:0]# 2.0 0.8 1.4 7.1 ns (3) t27 sbcerr# 1.2 5.5 ns (3) memory interface signalsmic t28 micmwc# ? write cycle 4.3 0.5 ns t29 miccmd[6:0]# 5.2 0.6 ns t30 mdrdy# 5.6 0.4 ns t31a mde[17:0] ? write cycle 4.7 0.5 ns t31b mde[17:0] delay ? read cycle 1.8 8.0 ns (3) (5) sym parameter setup min hold min delay min delay max unit notes
preliminary 159 a pciset electrical specifications 1. min timings are measured with 0pf load, max timings are measured with 50pf load. 2. min and max timings are measured with a 50pf load. 3. min and max timings are measured with 0pf load. 4. t22 and t23 apply to the intel 450kx pciset, signals casb[3:0]#, casa[3:0]#, rasb[3:0]#, rasa[3:0]#. 5. see figure 7. 6. the power supply must wait until all voltages are stable for at least 1ms, and then assert the pwrgd signal. 7. inputs are referenced to tck rising, outputs are referenced to tck falling. t31c mde[17:0] flow through during window ? read cycle 1.7 7.5 ns (3) (5) t31d mde[17:0] flow through pre-window ? read cycle 1.9 9.0 ns (3) (5) t31e window start time from bclk rising ? read cycle 2.0 ns (3) (5) t31f window end time after bclk rising ? read cycle 0.5 ns (3) (5) t32a i[3:0]dx 1.2 1.3 ns (5) t32b i[3:0]dx delay ? write cycle 1.8 10.4 ns (3) t32c i[3:0]dx float delay 2.1 9.7 ns (3) memory control signals t33 sysden# 6.3 0.6 1.4 6.8 ns (3) t34 dc-to-dp: syscmd[4:0]# 2.3 0.8 1.1 7.4 ns (3) t35 dp-to-dc: memerr[1:0]#, syserr# 3.2 0.8 1.2 5.3 ns (3) t36 omcnum 3.3 0.3 ns reset signals t39 mirst# 2.9 0.6 1.3 5.5 ns (3) t40 creset# 2.0 10.0 ns (3) t41 smiact# 2.0 12.0 ns (3) t42 pwrgd inactive pulse 10 clks bus clocks (6) testability signals t45 trst# ns async. t46 tms 4.6 0.8 ns (7) t47 tdi 6.0 2.0 ns (7) t48a tdo 1.2 16.0 ns (3) (7) t48b tdo on/off delay 1.4 16.0 ns (3) (7) non-gtl+ host bus signals t49 init#, flush# 2.0 12.0 ns (3) table 10. ac specifications (cmos signals) (continued)
160 preliminary pciset electrical specifications a 1.5.1 waveforms gtl+ signal waveforms: please see the pentium pro family developers manual: specifications for more infor- mation on gtl+ clock, setup, hold, and valid delay waveforms. pci bus signal waveforms: all pci bus signals are referenced to the pclkin rising edge. for more infor- mation on the pci bus signals and waveforms, please refer to the pci specification 2.0 . figure 2. clock waveform figure 3. valid delay timings figure 4. setup & hold timings t high t low t rise t fall t period clk 2.0v 1.5v 0.8v clk va li d va li d v 1.5v t va lid signal t pulse _ width t va lid t hi t lo clk valid v 1.5v t setup signal t pulse _ width t hold
preliminary 161 a pciset electrical specifications figure 5. exception to gtl+ minimal input waveform with setup impact figure 6. example of 450kx/gx receiver waveform that benefits from t su derating 0 1 2 3 4 5 6 7 8 v ref - 200 mv v ref v ref + 100 mv v ref + 200 mv 3 ns time (ns) 0.3 v/ns edge rate for gtl+ waveforms that fall in the shaded region C setup min is derated 1 ns C t8 and t10 setup min = 5.5 ns v ref v ref + 100 mv v ref + 200 mv 30 32 34 36 38 40 time (ns) volatage (volts) note: 2ns additional flight time as per the gtl+ i/o specification. however, another option is to derate setup by 1ns as this meets the requirements for the exception.
162 preliminary pciset electrical specifications a figure 7. system memory signals [memory read (mic)] the read data window is shown in figure 7. at the first clock of a memory read cycle, data is valid to the mics either before or during the mics transparent latch window. if data is valid before the window, t31d timings apply. if data is valid during the window, t31c timings apply. t31b is t co of the 2 nd , 3 rd , and 4 th quad words. 2.0 signal quality the gtl+ i/o buffer specification defines new terms for use by buffer and system designers. these 450kx/gx pciset buffers are described in these terms within this section. see the pentium pro family developers manual: specifications for the complete explanation of these terms. 2.1 i/o signal simulationsensuring i/o timings it is highly recommended that system designers run extensive simulations on their pentium pro processor/450GX- or 450kx-based designs. in addition, these simulations should include the memory subsystem designl. please refer to the gtl+ guidelines application note , ap-524, and the pentium pro family developers manual: specifications for more information. for simulations, your field representative can provide the intel 450kx/gx pciset i/o buffer model specification . bclk nop miccmd# t window start mrd nop t31e t31f t window end i[3:0]dx mde i[3:0]dx mde t31d t32a t32a t31b t31c before window during window
preliminary 163 a pciset electrical specifications 2.2 signal quality specifications signals driven by any component on the pentium pro processor bus must meet signal quality specifications to guarantee that the components read data properly, and to ensure that incoming signals do not affect the long term reliability of the components. there are three signal quality parameters defined: overshoot/undershoot, ringback, and settling limit. these parameters are discussed in the next sections. 2.3 pciset ringback specification this section discusses the ringback specification for the parameters in the gtl+ signal groups on the intel 450kx/gx pcisets. case a requires less time than case b from the v ref crossing until the ringback into the overdrive region. the longer time from v ref crossing until the ringback into the overdrive region required in case b allows the ringback to be closer to v ref for a defined period. note: specified for an edge rate of 0.3C0.8 v/ns. see the pentium pro family developers manual for the definition of these terms. see the figures below for the generic waveforms. all values determined by design/characterization. notes: 1. specified for an edge rate of 0.3C0.8 v/ns. see the pentium pro family developers manual for the definition of these terms. see the figures below for the generic waveforms. all values determined by design/characterization. table 11. 450kx/gx gtl+ signal groups ringback tolerancecase a parameter min unit figure a : overshoot 100 mv 8, 9 t : minimum time at high or low 2.25 ns 8, 9 r : amplitude of ringback -100 mv 8, 9 d : duration of square-wave ringback n/a ns 8, 9 f : final settling voltage 100 mv 8, 9
164 preliminary pciset electrical specifications a notes: 1. specified for an edge rate of 0.3C0.8 v/ns. see the pentium pro family developers manual for the definition of these terms. see the figures below for the generic waveforms. all values determined by design/characterization. figure 8. standard input lo-to-hi waveform for characterizing receiver ringback tolerance table 12. 450kx/gx gtl+ signal groups ringback tolerancecase b parameter min unit figure a : overshoot 100 mv 8, 9 t 1 :minimum time at high 2.7 ns 8, 9 t 2 :minimum time at low 3.7 ns 8, 9 r : amplitude of ringback -0 mv 8, 9 d : duration of square-wave ringback 2 ns 8, 9 f : final settling voltage 100 mv 8, 9 v ref - 0.2 v ref v ref +0.2 v start 0 . 3 v / n s 0 . 8 v / n s clock tsu + 0.05 1.5 v clk ref 10 ps rise/fall edges time f r t d a
preliminary 165 a pciset electrical specifications figure 9. standard input hi-to-lo waveform for characterizing receiver ringback tolerance 2.4 450kx/gx undershoot specification the pentium pro processor bus signals aerr#, berr#, binit#, bnr#, hit#, and hitm# (only) are capable of sinking an 85ma current pulse at a 2.4% average time duty cycle. this is equivalent to -1.7v applied to a 20 w source in series with the device pin for 8 ns at 66 mhz with a utilization of 5%. figure 10. undershoot v ref - 0.2 v ref v ref +0.2 v start 0 . 3 v / n s 1 . 5 v / n s clock tsu + 0.05 1.5 v clk ref 10 ps rise/fall edges time f r t d a 0.5 ns (max) 3.4 v p-to-p (max) +1.7 v voltage source waveform -1.7 v 7.5 ns (max) v r dut undershoot test waveform voltage source impedance r = 20 w average duty cycle of 2.4% note: this test covers the ac operating conditions only.
166 preliminary pciset electrical specifications a 3.0 thermal specifications these tables show the power dissipation for the intel 450kx/gx pcisets in qfp and bga packages. 1. q ja and q jc at 0 lfm air flow. 2. q ja would be reduced by 12% at 100 lfm air flow. 3. q ja and q jc at 0 lfm air flow. 4. q ja would be reduced by 10% at 100 lfm air flow. 5. both components are 4 layers. 6. thermal data extracted from a 4?x4? four layer board with two planes. table 13. qfp package thermal specifications device max power in watts q ja c/w q jc c/w pb 304 qfp 2.40 18 5 dp 240 qfp 2.30 25 6 dc 208 qfp 1.13 35 7 mic 144 qfp 0.69 48 6 table 14. bga package thermal specifications device max power in watts q ja c/w q jc c/w pb 352 bga 2.40 18 6 dp 256 bga 2.30 20 5
preliminary 167 a index
168 preliminary a
a index preliminary 169 numerics 1m power-on reset vector 52 2-way dram configuration 129 4-way dram configuration 128 a absolute maximum ratings 153 ac specifications 157 cmos 158 gtl+ 157 address bit permuting 109 aerr# 19 , 52 , 54 , 62 , 121 aliasing 12 , 38 , 59 anomaly 73 apic cluster id 51 , 52 apicri/o apic range register 50 , 115 b baseaddmc base address register 107 bclk 22 , 70 , 157 bdnumbridge device number register 39 berr# 19 , 52 , 54 , 121 binit# 19 , 54 , 62 , 73 , 121 bios 9 , 69 bios range 53 bist 29 , 37 , 72 bist register 37 block diagram 4 pci bridge 18 blocking logic 75 bpri# 19 , 66 bridge arbitration 41 bridge to bridge sideband signals 22 bridge-to-bridge communication 67 burst write assembly 42 bus number 28 , 30 , 39 , 103 bus protocol violation 55 c cache line size 36 capacitance 155 , 156 cdnumcontroller device number register 108 classcclass code register 36 , 107 clock 70 , 131 , 157 clock distribution 70 , 131 clsizecache line size register 36 cmdcommand register 108 command translation 76 common cas# 109 , 127 compatibility 8 confadd register 27 , 28 , 101 , 102 confdata register 27 , 30 , 101 , 102 configuration 26 , 70 , 72 , 101 memory 122 pci bridge registers 32 system 68 confvrconfiguration values driven on reset register 51 controller number 101 crwccpu read/write control register 41 csconfvcaptured system configuration values register 52 current 154 d data integrity 62 dc specifications 154 dccdeturbo counter register 41 deturbo 29 , 41 device number 28 , 31 , 39 , 103 , 108 device numbers 102 diddevice identification register 34 , 105 dimensions 87 , 145 dram interface 125 dram row limit 111 , 124 drldram row limit 111 dual address 78 dual pb 65 alphabetized index
index a 170 preliminary e ecc 62 , 116 efficiency 6 eisa 5 , 10 electrical specifications 151 errcmderror reporting command regis- ter 45 error 54 , 113 , 120 error handling 62 errstserror reporting status register 45 exerrcmdpb extended error reporting command register 53 exerrstspb extended error reporting status 55 extended memory 12 f fast back-to-back 35 flshbf# 21 flush# 20 frame buffer 9 , 47 , 58 frc mode 52 function number 29 , 103 g graphics adapter memory region 8 gtl+ 155 gtlrefv 22 h hard failure 55 hard reset 26 , 29 , 72 hbiosrhigh bios gap range register 119 hbiosrhigh bios range register 53 headtheader type register 37 hmgeahigh memory gap end address register 48 , 115 hmgsahigh memory gap range start address register 48 hmgsahigh memory gap start address register 115 host bus interface signals 19 host bus time-out 54 host-to-pci write posting 41 i i/o apic 51 , 58 , 115 , 124 configuration space 11 multiple 65 i/o map 57 , 123 i/o space 12 , 27 , 49 , 50 , 102 inbound posting 42 inbound queue 6 init on shutdown 40 initialization 26 , 72 , 101 in-order queue 6 , 62 in-order queue depth 52 , 108 interleave 5 , 125 iognt# 22 , 65 ioreq# 22 , 65 iosr1i/o space range 1 register 49 iosr2i/o space range 2 register 50 isa 5 , 9 isa alias mode 12 , 38 , 59 l latency-sensitive peripherals 68 leakage 155 , 156 line read 42 line read pre-fetch 42 livelock 69 lmglow memory gap register 114 lock atomic reads 40 locks 20 , 61 m master abort 29 , 35 , 54 , 63 master latency timer 37 , 70 maximum ratings 153 memack# 21 memory gap 5 , 57 , 113 , 123 memory interface component 127 memory map 7 , 57 , 123 memory mapped i/o 13 , 58 memory read line 77 memory size algorithm 122 memory sizes 126 memory space gap 46 memory timing register 116 memory write and invalidate 34 , 78 memtimmemory timing register 116 merrcmdmemory error reporting com- mand 120
a index preliminary 171 merrstsmemory error status register 120 mgmemory gap register 113 mgrmemory gap range register 46 mguamemory gap upper address register 46 , 114 n nmi 54 non-interleaved dram configuration 130 o omcnum 101 , 108 outbound posting 41 outbound request queue 6 overshoot 163 , 164 p p2p bridges 69 package 79 , 132 package dimensions 145 page open policy 109 pamprogrammable attribute map register 44 , 110 parity error 34 , 35 , 45 , 55 , 62 , 122 pbcpb configuration register 40 pbnumpci bus number register 39 pbrtmrpb retry timers 56 pci bridge 17 pci bus reset 72 pci configuration space 30 pcicmdpci command register 34 , 106 pcirsrpci reset register 49 pcistspci status register 35 , 106 pci-to-host bus write posting 42 pci-to-pci bridge 69 pci-to-pci bridges 69 pclk 157 pclkin 70 pdmpci decode mode 38 performance 68 , 69 peripherals 68 pfbpci frame buffer register 47 pinout 79 , 132 pltmrpci latency timer 37 posting 56 power specifications 154 prefetch enable 69 protocol violation 122 prwcpci read/write control 42 psbnumsubordinate bus number register 40 pwrgd 70 , 152 r read burst delay 109 read multiple 77 read/write clear 26 read-around-write 109 reclaim enable 113 reference voltage 155 refresh 117 , 126 register number 29 , 103 registers 26 , 101 request parity 62 reserved bits 26 , 101 reset 23 , 25 , 26 , 29 , 49 , 51 , 70 , 71 , 117 , 131 resource locks 61 retry counter 56 retry timers 56 revision identification 36 ridrevision identification register 36 , 106 ringback 163 row 125 s serr# 34 , 45 , 54 , 62 , 64 serrcmdsystem error reporting com- mand register 121 serrstssystem error status register 122 settling voltage 163 , 164 shutdown 45 signal groups 151 signal quality 163 signals 19 simulations 162 smi# 60 smiact# 20 smm 8 , 12 , 43 , 53 , 58 , 110 , 119 , 123 smmesmram enable register 110 smmrsmram range register 53 , 119
index a 172 preliminary smramsmm enable register 43 snoop phase 60 soft reset 29 , 72 special cycles 61 t target abort 35 , 45 , 61 , 63 target disconnect 63 target retry 63 targeted pci resets 74 tck 157 temperature specification 154 termination voltage 155 test signals 151 thermal specifications 166 time-out 54 , 62 trcturbo and reset control 29 tsmtop of system memory register 38 u uerradduncorrectable error address register 116 undershoot 165 unused pins 151 v vbaevideo buffer area enable register 43 vbrevideo buffer region enable register 110 video buffer 57 , 123 video buffer area 43 , 110 vidvendor identification register 34 , 105 voltage 154 w watchdog timer 40 , 62 write back 60 write combining 60

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